DM74LS166

DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register August 1986 Revised March 2000 DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register General Description These parallel-in or serial-in, serial-out shift registers feature gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching transients to simplify system design. The load mode is established by the shift/load input. When HIGH, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When LOW, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the LOW-to-HIGH level edge of the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking; holding either LOW enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. Ordering Code: Order Number Package Number Package Description DM74LS166M M16A ...