GS8342Q36E-300

Preliminary GS8342Q08/09/18/36E-300/250/200/167 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaQuad-II Burst of 2 SRAM 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Simultaneous Read and Write SigmaQuad™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices SigmaQuad™ Family Overview The GSQ8342Q08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GSQ8342Q08/09/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GSQ8342Q08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows ...