Document
NB3N4666C
3.3 V Quad LVCMOS Differential Line Receiver Translator
Description The NB3N4666C is a quad−channel LVDS line receiver/translator
offering data rates up to 400 Mbps (200 MHz) and low power consumption. The NB3N4666C receiver incorporates input fail−safe protection circuit that provides a known output voltage under input open−circuit, short and terminated (100 W) conditions. The four independent inputs accept differential signals such as: M−LVDS, LVDS, LVPECL and HCSL and translates them to a single−ended, 3.3 V LVCMOS.
The NB3N4666C also offers active high and active low enable/disable inputs (EN and EN) that allow users to control outputs of all four receivers. These inputs enable or disable the receivers and switch the outputs to an active or high impedance state respectively (see Table 2). The high impedance mode feature helps to reduce the quiescent power consumption to less than 10 mW typical, when the outputs of one or more NB3N4666C devices are multiplexed together.
Features
• Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input
Signal Levels
• Maximum Data Rate of 400 Mbps • Maximum Clock Frequency of 200 MHz • 25 ps Typical Channel−to−Channel Skew • 3.3 ns Maximum Propagation Delay • 3.3 V ±10% Power Supply • High Impedance Outputs When Disabled
♦ Low Quiescent Power < 10 mW Typical
• Supports Open, Short, and Terminated Input Fail−safe • −40°C to +85°C Ambient Operating Temperature • 16−Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm • These are Pb−Free Devices
Applications
• Point−to−point Data Transmission • Backplane Receivers • Clock Distribution Networks • Multidrop Buses
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TSSOP−16 DT SUFFIX CASE 948F
MARKING DIAGRAMS
16 NB3N 4666 ALYWG G
1
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
(Note: Microdot may be in either location)
IN1 IN1
OUT1 EN
NB3N4666C R1 R4
VCC IN4 IN4
OUT4 EN
OUT2
OUT3
R2 R3
IN2 IN2 GND
IN3 IN3
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
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Publication Order Number: NB3N4666C/D
NB3N4666C
Table 1. PIN DESCRIPTION
Pin TSSOP
Name
I/O
Description
1 IN1
Input
Receiver Channel 1 Inverted Input.
2 IN1
Input
Receiver Channel 1 Non−inverted Input.
3
OUT1
LVCMOS Output Receiver Channel 1 Output.
4
EN
Input Enable
Active High Enable. See Table 2 for output enable function.
5
OUT2
LVCMOS Output Receiver Channel 2 Output.
6 IN2
Input
Receiver Channel 2 Non−inverted Input.
7 IN2
Input
Receiver Channel 2 Inverted Input.
8
GND
Power
Power Supply Ground (Note 1)
9 IN3
Input
Receiver Channel 3 Inverted Input.
10 IN3
Input
Receiver Channel 3 Non−inverted Input.
11
OUT3
LVCMOS Output Receiver Channel 3 Output.
12 EN Inverted Input Active Low Enable. Defaults Low when left open; internal pull−down resistor.
Enable
See Table 2 for output enable function.
13
OUT4
LVCMOS Output Receiver Channel 4 Output.
14 IN4
Input
Receiver Channel 4 Non−inverted Input.
15 IN4
Input
Receiver Channel 4 Inverted Input.
16 VCC
Power
3.3 V ±10% Positive Supply Voltage (Note 1)
1. All VCC and GND pins must be externally connected to a power supply for proper operation. Bypass each supply pin with 0.01 mF to GND.
IN1 1 IN1 2 OUT1 3 EN 4 OUT2 5 IN2 6 IN2 7 GND 8
16 VCC 15 IN4 14 IN4 13 OUT4 12 EN 11 OUT3 10 IN3 9 IN3
Figure 2. TSSOP−16 Pinout (Top View)
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NB3N4666C
Table 2. OUTPUT ENABLE FUNCTION
ENABLES
INPUTS
EN EN
IN, IN
LH
X
All other combinations of ENABLE inputs
VID ≥ 100 mV
VID ≤ −100 mV
Full Fail−safe OPEN/SHORT or Terminated
OUTPUT OUT Z H L H
VID, DIFFERENTIAL INPUT VOLTAGE (mV)
200 mV 100 mV
High
0 mV
Transition Region
−100 mV −200 mV
Low
Figure 3. Receiver Differential Input Voltage Showing Transition Region
Table 3. ATTRIBUTES (Note 2)
Characteristics
ESD Protection
Human Body Model
Charged Device Model
CIN − Input Capacitance RIN − Input Impedance RPD − Inverted Input Enable Pull−down Resistor Moisture Sensitivity
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value 6 kV 500 V 4 pF typical > 10 kW 800 kW Level 1 UL 94 V−0 @ 0.125 in 621
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NB3N4666C
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC Supply Voltage Range VIN Input Voltage Range TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient)
GND = 0 V GND = 0 V
0 lfpm 500 lfpm
TSSOP−16 TSSOP−16
4.6 −0.5 to VCC +0.5
−40 to +85 −65 to +150
138 108
V V °C °C °C/W
qJC Thermal Resistance (Junction−to−Case)
2S2P
TSSOP−16
33−36
°C/W
Tsol Wave Solder (Pb−Free)
265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceede.