TTR011

TONTEK DESIGN TECHNOLOGY LTD. Title TTR011 (1K ROM MCU) Version 3.2 Preliminary Page 1 of 41 TTR011 § Features ◆ Tontek RISC 4-bit CPU core with 2-level stacks ◆ All instructions are one word length ◆ Most of instructions need one machine cycle (2 CPU clocks) except read table instruction RTB ◆ Advanced CMOS process ◆ 1Kx16 OTP ROM ◆ 56x4 SRAM ◆ Operating voltage: 2.0V~5.50V ◆ Two high-speed clock OSCH selectable: on-chip 910kHz oscillator, external RC oscillator ◆ One low-speed clock OSCL: on-chip 16kHz oscillator ◆ Power-on default is low speed mode ◆ Four operation modes - STOP mode: CPU, OSCH and OSCL stop - GREEN mode: CPU and OSCH stop; OSCL active for periodical ADC measure and wake-up - Low power mode: OSCH stop, OSCL active for CPU and peripheral circuit - Normal mode: Both OSCH and OSCL active, CPU clock from OSCH ◆ 11 I/O pins + 1 input - PA, PB and PC can be configured as wake-up input pins - PB and PC can be programmed as input pins with pull-high resistors - Four input pins can be defined as external interrupt input pins - Shared with 5 ADC input channels and 1 buzzer output ◆ 5-channel 4-bit ADC ◆ One time base timer - In GREEN mode, its clock is from the overflow of timer/counter B and its overflow wake up CPU from GREEN mode. - In other mode, its clock is from OSCL ◆ Two 8-bit timer/counter - One 8-bit timer/counter B with two sets of auto-preload data to generate periodic waveform for buzzer function. - In GREEN mode, the overflow of timer B will trigg...