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NP16N06QLK Dataheets PDF



Part Number NP16N06QLK
Manufacturers Renesas
Logo Renesas
Description Dual N-Channel Power MOSFET
Datasheet NP16N06QLK DatasheetNP16N06QLK Datasheet (PDF)

NP16N06QLK 60 V – 16 A – Dual N-channel Power MOS FET Application: Automotive Data Sheet R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Description NP16N06QLK is a dual N-channel MOS Field Effect Transistor designed for high current switching applications. Features  Super low on-state resistance  RDS(on)1 = 39 m MAX. (VGS = 10 V, ID = 8 A)  RDS(on)2 = 60 m MAX. (VGS = 4.5 V, ID = 4 A)  Low Ciss: Ciss = 500 pF TYP. (VDS = 25 V)  Designed for automotive application and AEC-Q101 qualified  Small .

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NP16N06QLK 60 V – 16 A – Dual N-channel Power MOS FET Application: Automotive Data Sheet R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Description NP16N06QLK is a dual N-channel MOS Field Effect Transistor designed for high current switching applications. Features  Super low on-state resistance  RDS(on)1 = 39 m MAX. (VGS = 10 V, ID = 8 A)  RDS(on)2 = 60 m MAX. (VGS = 4.5 V, ID = 4 A)  Low Ciss: Ciss = 500 pF TYP. (VDS = 25 V)  Designed for automotive application and AEC-Q101 qualified  Small size package 8-pin HSON dual Outline Remark: Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Ordering Information Part No. Lead Plating Packing NP16N06QLK-E1-AY *1 Pure Sn (Tin) Tape 2500 p/reel Taping (E1 type) NP16N06QLK-E2-AY *1 Taping (E2 type) Note: *1. Pb-free (This product does not contain Pb in the external electrode) Package 8-pin HSON dual R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Page 1 of 7 NP16N06QLK Absolute Maximum Ratings (TA = 25°C) Item Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25C) 4 Drain Current (pulse) 1, 4, 5 Total Power Dissipation (TC = 25C) 4 Total Power Dissipation (TA = 25C) 2, 4 Channel Temperature Storage Temperature Repetitive Avalanche Current 3, 5 Repetitive Avalanche Energy 3, 5 Symbol VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg IAR EAR Ratings 60 ±20 ±16 ±32 25 1.0 175 55 to 175 7 5 Unit V V A A W W C C A mJ Thermal Resistance Channel to Case Thermal Resistance Channel to Ambient Thermal Resistance 2 Rth(ch-C)*5 Rth(ch-A) *5 5.95 150 C/W C/W Notes: *1. TC = 25°C, PW  10 s, Duty Cycle  1% *2. Mounted on glass epoxy substrate of 40 mm  40 mm  1.6 mmt with 4% copper area (35 m) *3. RG = 25 , VGS = 20 V  0 V *4. One channel operation *5. Not subject of production test. Verified by design/characterization. R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Page 2 of 7 NP16N06QLK Electrical Characteristics (TA = 25°C) Item Symbol Min Typ Max Zero Gate Voltage Drain Current IDSS 1 Gate Leakage Current IGSS ±10 Gate to Source Threshold Voltage VGS(th) 1.5 2.1 2.5 Forward Transfer Admittance 1 | yfs | 5 13 Drain to Source On-state Resistance 1 RDS(on)1 RDS(on)2 30 39 38 60 Input Capacitance *2 Ciss 500 750 Output Capacitance *2 Coss 50 75 Reverse Transfer Capacitance *2 Crss 30 54 Turn-on Delay Time *2 td(on) 15 30 Rise Time *2 tr 5 13 Turn-off Delay Time *2 td(off) 30 60 Fall Time *2 tf 3 8 Total Gate Charge *2 QG 11 17 Gate to Source Charge QGS 3 Gate to Drain Charge Body Diode Forward Voltage 1 QGD VF(S-D) 3 0.9 1.5 Reverse Recovery Time trr 20 Reverse Recovery Charge Qrr 16 Note: *1. Pulsed test Note: *2. Not subject of production test. Verified by design/characterization. Unit A A V S m m pF pF pF ns ns ns ns nC nC nC V ns nC Test Conditions VDS = 60 V, VGS = 0 V VGS = ±20 V, VDS = 0 V VDS = VGS, ID = 250 A VDS = 5 V, ID = 8 A VGS = 10 V, ID = 8 A VGS = 4.5 V, ID = 4 A VDS = 25 V, VGS = 0 V, f = 1 MHz VDD = 30 V, ID = 8 A, VGS = 10 V, RG = 0  VDD = 48 V, VGS = 10 V, ID = 16 A IF = 16 A, VGS = 0 V IF = 16 A, VGS = 0 V, di/dt = 100 A/s R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Page 3 of 7 NP16N06QLK Typical Characteristics (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 120 dT - Percentage of Rated Power - % 100 80 60 40 20 0 0 50 100 150 200 TC - Case Temperature - C FORWARD BIAS SAFE OPERATING AREA 100 ID (pulse)= 3 2 A 10 ID (D C)= 1 6 A Pt – Total Power Dissipation - W 30 25 20 15 10 5 0 0 TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 50 100 150 200 TC - Case Temperature - C ID - Drain Current - A 1 Power Dissipation Lim ited 0.1 TC=25℃ Single Pulse 0.01 0.1 1 10 100 VDS - Drain to Source Voltage – V 1000 100 TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH R th(ch-A) = 150°C/W Rth(t) - Transient Thermal Resistance - C/W 10 R th(ch-C) = 5.95°C/W 1 0.1 100  One channel operation Single pulse Mounted on a glass expoxy substrate of 40mm x 40mm 1.6 mmt with 4% Copper Area(35m) 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s R07DS1290EJ0200 Rev. 2.00 May 24, 2018 Page 4 of 7 RDS(on) - Drain to Source On-state Resistance - m VGS(th) – Gate to Source Threshold Voltage - V ID - Drain Current - A NP16N06QLK DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 35 30 25 20 15 10 5 0 0 VGS=10V Pulsed 0.2 0.4 0.6 0.8 1 1.2 VDS - Drain to Source Voltage - V GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE 4 3 2 1 VDS = VDS ID=250A 0 -100 -50 0 50 100 150 200 Tch - Channel Temperature - .


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