Document
H5PS5162FFR Series
512Mb DDR2 SDRAM
H5PS5162FFR-xxC H5PS5162FFR-xxI H5PS5162FFR-xxL H5PS5162FFR-xxJ
[New Product] H5PS5162FFR-xxP H5PS5162FFR-xxQ
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Sep. 2010
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H5PS5162FFR series
Revision History
Rev. 1.0 1.1
History Release Insert DDR2-1066 & modify DDR2-800 tFAW value
Draft Date Jul. 2008 Sep. 2010
Rev.1.1 / Sep. 2010
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Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description
2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition
3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
H5PS5162FFR series
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features • VDD ,VDDQ =1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 3, 4, 5 and 6 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4 / 8 with both nibble sequential and interleave mode • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 84ball FBGA(x16) : 8mm x 13mm • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Self-Refresh High Temperature Entry • Partial Array Self Refresh support
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
Ordering Information
Part No. H5PS5162FFR-xx*C H5PS5162FFR-xx*I
Configuration
Power Consumption
Normal Consumption Normal Consumption
Operation Temp
Commercial Industrial
Package
H5PS5162FFR-xx*L
H5PS5162FFR-xx*J H5PS5162FFR-xx*P H5PS5162FFR-xx*Q
32Mx16
Low Power Consumption (IDD6 Only)
Low Power Consumption (IDD6 Only)
Low Current Consumption
Low Current Consumption
Commercial
Industrial Commercial Industrial
84 Ball fBGA
Note:
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-xxP and xxQ are the low current bin, refer to the IDD specification table. - Hynix Halogen-free products are compliant to RoHS. Hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials. We'll add "R" character after "F" for Lead & Halogen free products
Operating Frequency
Grade E3 C4 Y5 S6 S5 G7
Note:
tCK(ns) 5
3.75 3 2.5 2.5
1.875
CL 3 4 5 6 5 7
tRCD 3 4 5 6 5 7
tRP 3 4 5 6 5 7
Unit Clk Clk Clk Clk Clk Clk
-G7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer digital electronic device. - x16 product only
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
1.2 Pin Configuration & Address Table
32Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
123 VDD NC VSS
789
A
VSSQ
UDQS
VDDQ
DQ14
VSSQ
UDM
B
UDQS
VSSQ
DQ15
VDDQ DQ9 VDDQ C VDDQ DQ8 VDDQ
DQ12
VSSQ
DQ11
D
DQ10
VSSQ
DQ13
VDD NC VSS
E
VSSQ
LDQS
VDDQ
DQ6 VSSQ LDM
F
LDQS
VSSQ
DQ7
VDDQ DQ1 VDDQ G VDDQ DQ0 VDDQ
DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5
VDDL
VREF CKE
VSS WE
J
VSSDL
CK
K RAS CK
VDD ODT
NC BA0 BA1 L CAS CS
A10 A1 M A2 A0 VDD
VSS A3
A5
N
A6 A4
A7 A9
P A11 A8 VSS
VDD
A12
NC
R
NC NC
ROW AND COLUMN ADDRESS TABLE
ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size
32Mx16 4
BA0, BA1 A10/AP A0 - A12 A0-A9
2 KB
Rev.1.1 / Sep. 2010
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H5PS5162FFR series
1.3 PIN DESCRIPTION
PIN TYPE
DESCRIPTION
CK, CK
CKE
CS ODT RAS, CAS, WE DM (LDM, UDM) BA0 - BA1
A0 -A12 DQ
Input
Clock: CK and CK are differential clock inp.