Document
MM54HC190 MM74HC190 MM54HC191 MM74HC191
January 1988
MM54HC190 MM74HC190 Synchronous
Decade Up Down Counters with Mode
Control MM54HC191 MM74HC191
Synchronous Binary Up Down Counters
with Mode Control
General Description
These high speed synchronous counters utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of CMOS technology along with the speeds of low power Schottky TTL
These circuits are synchronous reversible up down counters The MM54HC191 MM74HC191 are 4-bit binary counters and the MM54HC190 MM74HC190 are BCD counters Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters
The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits counting The direction of the count is determined by the level of the down up input When low the counter counts up and when high it counts down
These counters are fully programmable that is the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs The output will change independent of the level of the clock input This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the preset inputs
Two outputs have been made available to perform the cascading function ripple clock and maximum minimum count The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used or to the clock input if parallel enabling is used The maximum minimum count output can be used to accomplish look-ahead for high-speed operation
Features
Y Level changes on Enable or Down Up can be made regardless of the level of the clock input
Y Wide power supply range 2 – 6V Y Low quiescent supply current 80 mA maximum
(74HC Series) Y Low input current 1 mA maximum
Connection Diagram
Dual-In-Line Package
Load
H H L H
Enable G
L L X H
Down Up
L H X X
Clock Function
u Count Up u Count Down
X Load X No Change
Asynchronous inputs Low input to load sets QA e A QB e B QC e C and QD e D
Order Number MM54HC190 191 or MM74HC190 191
Top View
C1995 National Semiconductor Corporation TL F 5322
TL F 5322 – 1
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Notes 1 2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD)
(Note 3) S O Package only
b0 5 to a7 0V b1 5 to VCCa1 5V b0 5 to VCCa0 5V
g20 mA g25 mA g50 mA b65 C to a150 C
600 mW 500 mW
Lead Temp (TL) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (VCC)
DC Input or Output Voltage (VIN VOUT)
Operating Temp Range (TA) MM74HC MM54HC
Min 2 0
b40 b55
Input Rise or Fall Times
(tr tf)
VCCe2 0V VCCe4 5V VCCe6 0V
Max 6
VCC
a85 a125
1000 500 400
Units V V
C C
ns ns ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C Typ
74HC
54HC
TAeb40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
VIH Minimum High Level Input Voltage
V V V
V V V
VIL Maximum Low Level Input Voltage
V V V
V V V
VOH
Minimum High Level VINeVIH or VIL
Output Voltage
lIOUTls mA
V V V
V V V
VINeVIH or VIL
lIOUTls mA lIOUTls mA
VOL Maximum Low Level VINeVIH or VIL
Output Voltage
lIOUTls mA
V V
V V V
V V
V V V
VINeVIH or VIL
lIOUTls mA lIOUTls mA
V V
IIN
Maximum Input
VINeVCC or GND
V
Current
g
g
V V
g mA
ICC
Maximum Quiescent VINeVCC or GND
V
Supply Current
IOUTe mA
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst c.