PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B
2M x 36 and 4M x 18
JULY 2019
72Mb, PIPELINE '...
Description
IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B
2M x 36 and 4M x 18
JULY 2019
72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address,
data and control Interleaved or linear burst sequence control us-
ing MODE input Three chip enables for simple depth expansion
and address pipelining Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP, 165-ball PBGA and 119-
ball PBGA packages Power supply:
NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%) JTAG Boundary Scan for PBGA packages Industrial temperature available Lead-free available
FAST ACCESS TIME
Symbol tkq tkc
Parameter Clock Access Time Cycle Time Frequency
250
200
2.8
3.1
4
5
250
200
DESCRIPTION
The 72 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to writ...
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