DatasheetsPDF.com

IS61DDB22M18A Dataheets PDF



Part Number IS61DDB22M18A
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
Datasheet IS61DDB22M18A DatasheetIS61DDB22M18A Datasheet (PDF)

IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and .

  IS61DDB22M18A   IS61DDB22M18A



Document
IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.  Registered addresses, write and read controls, byte writes, data in, and data outputs.  Full data coherency.  Boundary scan using limited set of JTAG 1149.1 functions.  Byte write capability.  Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor. DESCRIPTION The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:  Read/write address  Read enable  Write enable  Byte writes for first burst address  Data-in for first burst address The following are registered on the rising edge of the K# clock:  Byte writes for second burst address  Data-in for second burst address Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the C# clock (starting one and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. B 10/02/2014 1 IS61DDB22M18A IS61DDB21M36A Package ballout and description x36 FBGA Ball Configuration (Top View) 1234567 A CQ# NC/SA1 SA R/W# BW2# K# BW1# B NC DQ27 DQ18 SA BW3# K BW0# C NC NC DQ28 VSS SA SA0 SA D NC DQ29 DQ19 VSS VSS VSS VSS E NC NC DQ20 VDDQ VSS VSS VSS F NC DQ30 DQ21 VDDQ VDD VSS VDD G NC DQ31 DQ22 VDDQ VDD VSS VDD H Doff# VREF VDDQ VDDQ VDD VSS VDD J NC NC DQ32 VDDQ VDD VSS VDD K NC NC DQ23 VDDQ VDD VSS VDD L NC DQ33 DQ24 VDDQ VSS VSS VSS M NC NC DQ34 VSS VSS VSS VSS N NC DQ35 DQ25 VSS SA SA SA P NC NC DQ26 SA SA C SA R TDO TCK SA SA SA C# SA Notes: 1. The following balls are reserved for higher densities: 10A for 72Mb and 2A for 144Mb. 8 LD# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA x18 FBGA Ball Configuration (Top View) 12345678 A CQ# NC/SA1 SA R/W# BW1# K# NC/SA1 LD# B NC DQ9 NC SA NC/SA1 K BW0# SA C NC NC NC VSS SA SA.


IS61DDB251236A IS61DDB22M18A IS61DDB21M36A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)