36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M18A IS61DDB21M36A
2Mx18, 1Mx36
36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
JANUARY 2015
FEATURES
1Mx36 and ...
Description
IS61DDB22M18A IS61DDB21M36A
2Mx18, 1Mx36
36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
JANUARY 2015
FEATURES
1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid
window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write
operation. Double Data Rate (DDR) interface for read and
write input ports. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control
registering at rising edges only. Two input clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ,
used with 0.75V to 0.9V VREF. HSTL input and output interface. Registered addresses, write and read controls, byte
writes, data in, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 1149.1
functions. Byte write capability. Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor.
DESCRIPTION
The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for ...
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