IS61DDB22M18

36 Mb (1M x 36. & 2M x 18) ISSIDDR-II (Burst of 2) CIO Synchronous SRAMs ® Features 1M x 36 or 2M x 18. On-chip delay-locked loop (DLL) for wide data valid window. Common data input/output bus. Synchronous pipeline read with self-timed late write operation. Double data rate (DDR-II) interface for read and write input ports. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K) for address and control registering at rising edges only. Two input clocks (C and C) for data output control. May 2005 Two echo clocks (CQ and CQ) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. HSTL input and output levels. Registered addresses, write and read controls, byte writes, data in, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 1149.1 functions. Byte write capability. Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor. Description The 36Mb IS61DDB21M36 and IS61DDB22M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operati...