72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.0 Cycle Read Late...
Description
IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
NOVEMBER 2014
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Common I/O read and write ports. Synchronous pipeline read with self-timed late write
operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
+1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75 to 0.9V VREF.
HSTL input and output interface. Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency. Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability. Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array
Programmable impedance output drivers via 5x user-supplied precision resistor.
Data Valid Pin (QVLD). ODT (On Die Termination) feature is supported
optionally on data inputs, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options.
IS61DDP2B42M36A : Don’t care ODT function and pin connection
IS61DDP2B42M36A1 : Option1 IS61DDP2B42M36A2 : Option2 Refer to more detail des...
Similar Datasheet