Document
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs
(2.5 Cycle Read Latency)
Advanced Information May 2009
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Common data input/output bus. • Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-IIP) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Industrial temperature available upon request.
• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls, byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1 functions.
• Byte write capability.
• Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x user-supplied precision resistor.
Description
The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.
The input addresses are registered on all rising edges of the K clock. The DQ bus operates at double data rate for reads and writes. The following are registered internally on the rising edge of the K clock:
• Read and write addresses • Address load • Read/write enable
Byte writes • Data-in • Data-out
The following are registered on the rising edge of the K clock:
• Byte writes • Data-in for second burst addresses • Data-out
Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle later than the write address. The first data-in burst is clocked with the rising edge of the next K clock, and the second burst is timed to the following rising edge of the K clock.
During the burst read operation, at the first burst the data-outs are updated from output registers off the second rising edge of the K clock (2.5 cycles later). At the second burst, the data-outs are updated with the fourth rising edge of the corresponding K clock (see page 8).
The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
1
D72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
I3
x36 FBGA Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11
A CQ NC/SA* SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B
NC
DQ27
DQ18
SA
BW3
K
BW0
SA
NC
NC DQ8
C NC
NC DQ28 VSS
SA
NC
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC DQ16
E NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ14
H Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC DQ2
M NC
NC DQ34 VSS VSS VSS VSS VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS NC
NC DQ10
P NC
NC DQ26 SA
SA
NC
SA
SA
NC
DQ9
DQ0
R TDO
TCK
SA
SA
SA
NC
SA
SA
SA
TMS
TDI
* The following pins are reserved for higher densities: 2A for 144Mb
• BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17; BW2 controls writes to DQ18–DQ26; BW3 controls
writes to DQ27–DQ35.
x18 FBGA Pinout (Top View)
12345678
A CQ SA
SA
R/W
BW1
K NC/SA* LD
B NC
DQ9
NC
SA NC/SA* K
BW0
SA
C NC NC NC VSS SA NC SA VSS
D NC
NC DQ10 VSS VSS VSS VSS VSS
E NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
F NC DQ12 NC
VDDQ
VDD
VSS
VDD
VDDQ
G NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
H Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
L NC DQ15 NC VDDQ VSS
VSS
VSS
VDDQ
M NC NC NC VSS VSS VSS VSS VSS
N NC
NC DQ16 VSS
SA
SA
SA
VSS
P NC NC DQ17 SA SA NC SA SA
R TDO
TCK
SA
SA
SA
NC
SA
SA
* The following pin is reserved for higher densities: 7A for 144Mb, 5B for 288Mb.
• BW0 controls writes to DQ0–DQ8; BW1 controls writes to DQ9–DQ17
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS
11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
2 Integrated Silicon Solution, Inc.
Rev. 00A 03/31/08
ID72DMb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchro.