256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION
IS43R32800B
8Mx32 256Mb DDR Synchronous DRAM
PRELIMINARY INFORMATION MAY 2008
FEATURES • Vdd/Vddq=2.5V+0.2V (-5, -6,...
Description
IS43R32800B
8Mx32 256Mb DDR Synchronous DRAM
PRELIMINARY INFORMATION MAY 2008
FEATURES Vdd/Vddq=2.5V+0.2V (-5, -6, -75)
Double data rate architecture; two data transfers per clock cycle
Bidirectional, data strobe (DQS) is transmitted/ received with data
Differential clock input (CLK and /CLK)
DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
Commands entered on each positive CLK edge;
Data and data mask referenced to both edges of DQS
4 bank operation controlled by BA0, BA1 (Bank Address)
/CAS latency –2.0/2.5/3.0 (programmable)
Burst length - 2/4/8 (programmable)
Burst type - Sequential/ Interleave (programmable)
Auto precharge / All bank precharge controlled by A8
4096 refresh cycles/ 64ms (4 banks concurrent refresh)
Auto refresh and Self refresh
Row address A0-11/ Column address A0-7, A9SSTL_2 Interface
Package 144-ball FBGA
Available in Industrial Temperature
Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC)
DESCRIPTION:
IS43R32800B is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The IS43R32800B achieves very high speed clock rate up to 200 MHz. It is packaged in 144-ball FBGA.
KEY TIMING PARAMETERS
Parameter
-5 -6 -75 Unit
Cl...
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