256Mb Synchronous DRAM
IS43R16160
32Mx8, 16Mx16 256Mb Synchronous DRAM
FEATURES: • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75)
• Double data rate arc...
Description
IS43R16160
32Mx8, 16Mx16 256Mb Synchronous DRAM
FEATURES: Vdd =Vddq = 2.5V+0.2V (-5, -6, -75)
Double data rate architecture ; two data transfers per clock cycle.
Bidirectional , data strobe (DQS) is transmitted/ received with data
Differential clock input (CLK and /CLK)
DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
Commands entered on each positive CLK edge;
Data and data mask referenced to both edges of DQS
4 bank operation controlled by BA0 , BA1 (Bank Address)
/CAS latency -2.0 / 2.5 / 3.0 (programmable) ; Burst length -2 / 4 / 8 (programmable) Burst type -Sequential / Interleave (programmable)
Auto precharge/ All bank precharge controlled by A10
8192 refresh cycles / 64ms (4 banks concurrent refresh)
Auto refresh and Self refresh
Row address A0-12 / Column address A0-8(x16)
SSTL_2 Interface
Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch
Temperature Range: Commercial (0oC to +70oC)
PRELIMINARY INFORMATION OCTOBER 2008
DESCRIPTION:
IS43R16160 is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The device achieves very high speed clock rate up to 200 MHz.
KEY TIMING PARAMETERS
Parameter
-5 -6 -75 Unit
Clk Cycle Time
CA...
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