IS45VS16400L

IS42VS16400L IS45VS16400L 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ADVANCED INFORMATION APRIL 2012 FEATURES Clock frequency: 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single 1.8V power supply LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Self refresh modes Auto refresh (CBR) 4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 16ms (A2 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command OPTIONS Package: 54-ball TF-BGA (8mm x 8mm) Operating Temperature Range Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade A1 (-40oC to +85oC) Automotive Grade A2 (-40oC to +105oC) OVERVIEW ISSI's 64Mb Synchronous DRAM is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -75 Unit 7.5 ns 10 ns 1...