ADSP-SC573

SHARC+ Dual-Core DSP with ARM Cortex-A5 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM FEATURES Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range MEMORY Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices ADDITIONAL FEATURES Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for ARM TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT ARM® TrustZone® SECURITY DUAL CRC WATCHDOGS OTP MEMORY THERMAL MONITOR UNIT (TMU) PROGRAM FLOW SYS EVENT CORE 0 (GIC) SYS EVENT CORES 1-2 (SEC) TRIGGER ROUTING (TRU) CLOCK, RESET, AND P...