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IS43DR86400D Dataheets PDF



Part Number IS43DR86400D
Manufacturers ISSI
Logo ISSI
Description DDR2 DRAM
Datasheet IS43DR86400D DatasheetIS43DR86400D Datasheet (PDF)

IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency (CL) 3, 4, 5, and 6 supported • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3.

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IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 internal banks for concurrent operation • Programmable CAS latency (CL) 3, 4, 5, and 6 supported • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength, full and reduced strength options • On-die termination (ODT) JANUARY 2015 DESCRIPTION ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ADDRESS TABLE Parameter 64M x 8 32M x 16 Configuration 16M x 8 x 4 8M x 16 x 4 banks banks Refresh Count 8K/64ms 8K/64ms Row Addressing 16K (A0-A13) 8K (A0-A12) Column Addressing 1K (A0-A9) 1K (A0-A9) Bank Addressing BA0, BA1 BA0, BA1 Precharge A10 A10 Addressing OPTIONS • Configuration(s): 64Mx8 (16Mx8x4 banks) IS43/46DR86400D 32Mx16 (8Mx16x4 banks) IS43/46DR16320D • Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm) • Timing – Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5ns @CL=3 DDR2-400B • Temperature Range: Commercial (0°C ≤ Tc ≤ 85°C) Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C) Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C) Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C) Tc = Case Temp, Ta = Ambient Temp KEY TIMING PARAMETERS Speed Grade -25D -3D tRCD 12.5 15 tRP 12.5 15 tRC 55 55 tRAS 40 40 tCK @CL=3 5 5 tCK @CL=4 3.75 3.75 tCK @CL=5 2.5 3 tCK @CL=6 2.5 — Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential l.


IS43DR16320D IS43DR86400D IS46DR16320D


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