IS43DR32800A, IS43/46DR32801A
8Mx32 256Mb DDR2 DRAM
PRELIMINARY INFORMATION SEPTEMBER 2010
FEATURES Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ ...
