DDR2 DRAM
IS43/46DR81280C IS43/46DR16640C
128Mx8, 64Mx16 DDR2 DRAM
FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standa...
Description
IS43/46DR81280C IS43/46DR16640C
128Mx8, 64Mx16 DDR2 DRAM
FEATURES Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT)
ADVANCED INFORMATION
DESCRIPTION
MAY 2013
ISSI's 1Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter Configuration
Refresh Count
128M x 8
16M x 8 x 8 banks
8K/64ms
64M x 16
8M x 16 x 8 banks
8K/64ms
Row Addressing 16K (A0-A13) 8K (A0-A12)
Column Addressing
1K (A0-A9)
Bank Addressing BA0 - BA2
1K (A0-A9) BA0 - BA2
Precharge Addressing
A10
A10
OPTIONS Configuration(s):
128Mx8 (16Mx8x8 banks): IS43/46DR81280C 64Mx16 (8Mx16x8 banks): IS43/46DR16640C
Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm)
Timing...
Similar Datasheet