Addressable Latch. 54LS256 Datasheet

54LS256 Latch. Datasheet pdf. Equivalent

54LS256 Datasheet
Recommendation 54LS256 Datasheet
Part 54LS256
Description Dual 4-Bit Addressable Latch
Feature 54LS256; 54LS256 DM74LS256 Dual 4-Bit Addressable Latch June 1989 54LS256 DM74LS256 Dual 4-Bit Addressable .
Manufacture National Semiconductor
Datasheet
Download 54LS256 Datasheet




National Semiconductor 54LS256
June 1989
54LS256 DM74LS256
Dual 4-Bit Addressable Latch
General Description
The ’LS256 is a dual 4-bit addressable latch with common
control inputs these include two Address inputs (A0 A1)
an active LOW enable input (E) and an active LOW Clear
input (CL) Each latch has a Data input (D) and four outputs
(Q0 – Q3)
When the Enable (E) is HIGH and the Clear input (CL) is
LOW all outputs (Q0–Q3) are LOW Dual 4-channel demul-
tiplexing occurs when the CL and E are both LOW When
CL is HIGH and E is LOW the selected output (Q0 – Q3)
determined by the Address inputs follows D When the E
goes HIGH the contents of the latch are stored When op-
erating in the addressable latch mode (E e LOW CL e
HIGH) changing more than one bit of the Address (A0 A1)
could impose a transient wrong address Therefore this
should be done only while in the memory mode (E e CL e
HIGH)
Features
Y Serial-to-parallel capability
Y Output from each storage bit available
Y Random (addressable) data entry
Y Easily expandable
Y Active low common clear
Connection Diagram Logic Symbol
Dual-In-Line Package
TL F 9823–1
Order Number 54LS256DMQB
54LS256FMQB or DM74LS256N
See NS Package Number J16A
N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
A0 A1
Da Db
E
CL
Q0a – Q3a
Q0b – Q3b
Description
Common Address Inputs
Data Inputs
Common Enable Input (Active LOW)
Conditional Clear Input (Active LOW)
Side A Latch Outputs
Side B Latch Outputs
TL F 9823 – 2
C1995 National Semiconductor Corporation TL F 9823
RRD-B30M115 Printed in U S A



National Semiconductor 54LS256
Truth Table
Inputs
Outputs
CL E A0 A1
Q0
Q1
Q2
Q3
LHX
X
L
L
L
L
LLL
L
D
L
L
L
L LH
L
L
D
L
L
LLL
H
L
L
D
L
L LH H
L
L
L
D
HHX
X
Qtb1
Qtb1
Qtb1
HLL
L
D
Qtb1
Qtb1
HLH
L Qtb1
D
Qtb1
HLL
H
Qtb1
Qtb1
D
H
LH
H
Qtb1
Qtb1
Qtb1
tb1 e Bit time before address change or rising edge of E
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Mode Selection
Qtb1
Qtb1
Qtb1
Qtb1
D
E CL
Mode
L H Addressable Latch
H H Memory
L L Active HIGH 4-Channel Demultiplexers
H L Clear
Logic Diagram
Mode
Clear
Demultiplex
Memory
Addressable
Latch
TL F 9823 – 3
2



National Semiconductor 54LS256
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
ts (H)
th (H)
ts (L)
th (L)
ts (H)
ts (L)
tw (L)
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH Dn to E
Hold Time HIGH Dn to E
Setup Time LOW Dn to E
Hold Time LOW Dn to E
Setup Time HIGH or LOW
An to E
E Pulse Width LOW
Min
45
2
b55
20
0
15
0
0
17
54LS256
Nom
5
Max
55
07
b0 4
4
125
DM74LS256
Min Nom Max
4 75 5 5 25
2
08
b0 4
8
0 70
20
0
15
0
0
17
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
VOH
Input Clamp Voltage
High Level Output
Voltage
VCC e Min II e b18 mA
VCC e Min IOH e Max
VIL e Max
54LS
DM74
25
27
VOL Low Level Output
Voltage
VCC e Min IOL e Max
VIH e Min
54LS
DM74
IOL e 4 mA VCC e Min
DM74
II
Input Current Max
VCC e Max VI e 10V
Inputs
Input Voltage
E
IIH
High Level Input Current
VCC e Max VI e 2 7V
Inputs
E
IIL
Low Level Input Current
VCC e Max VI e 0 4V
Inputs
E
IOS Short Circuit
Output Current
VCC e Max
(Note 2)
54LS
DM74
b20
b20
ICC Supply Current
VCC e Max
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Typ
(Note 1)
34
0 35
0 25
Max
b1 5
04
05
04
01
02
20
40
b0 4
b0 8
b100
b100
25
Units
V
V
V
mA
mA
mA
mA
mA
3







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