IS42/45SM/RM/VM32400G
1M x 32Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM32400G are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply • Auto refresh and self refresh • All pins are compatible with LVCMOS interface • 4K refresh cycle / 64ms • Programmable Burst Length and Burst Type
• 1, 2, 4, 8 or Full Page for Sequential Burst • 4 or 8 for Interleave Burst • Programmable CAS Latency : 2,3 clocks • All inputs and outputs referenced to the positive edge of the system clock • Data mask function by DQM
• Internal 4 banks operation • Burst Read Single Write operation • Special Function Support
• PASR(Partial Array Self Refresh) • Auto TCSR(Temperature Compensated Self Refresh) • Programmable Driver Strength Control
• Full Strength or 1/2, 1/4, 1/8 of Full Strength • Deep Power Down Mode • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | Apr. 2012
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IS42/45SM/RM/VM32400G
Figure1: 90Ball FBGA Ball Assignment 1 23
456
7
8
9
A DQ26 DQ24 VSS
B DQ28 VDDQ VSSQ
C VSSQ DQ27 DQ25
D VSSQ DQ29 DQ30
E VDDQ DQ31 NC
F VSS DQM3 A3
G A4 A5 A6
H A7 A8 NC
J CLK CKE A9
K DQM1 NC
NC
L VDDQ DQ8 VSS
M VSSQ DQ10 DQ9
N VSSQ DQ12 DQ14
P DQ11 VDDQ VSSQ
R DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0
A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
[Top View]
Rev. A | Apr. 2012
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Table2: Pin Descriptions Pin
Pin Name
CLK System Clock
CKE /CS BA0~BA1
Clock Enable Chip Select Bank Address
A0~A11
/RAS, /CAS, /WE
DQM0~DQM3 DQ0~DQ31 VDD/VSS VDDQ/VSSQ NC
Address
Row Address Strobe, Column Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection
IS42/45SM/RM/VM32400G
Descriptions
The system clock input. All other inputs are registered to the SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity. Selects bank to be read/written during CAS activity.
Row Address Column Address Auto Precharge
: RA0~RA11 : CA0~CA7 : A10
RAS, CAS and WE define the operation. Refer function truth table for details.
Controls output buffers in read mode and masks input data in write mode. Data input/output pin. Power supply for internal circuits and input buffers. Power supply for output buffers. No connection.
Rev. A | Apr. 2012
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ROW DECODER ROW DECODER ROW DECODER ROW DECODER
CONTROL LOGIC COMMAND DECODER
Figure2: Functional Block Diagram
CLK CKE
CLOCK GENERATOR
ADDRESS
MODE REGISTER
EXTENDED MODE
REGISTER
TCSR PASR
ROW ADDRESS BUFFER & REFRESH COUNTER
/CS /RAS /CAS /WE
COLUMN ADDRESS BUFFER &
BURST COUNTER
IS42/45SM/RM/VM32400G
BANK D BANK C BANK B BANK A
SENSE AMPLIFIER COLUMN DECODER & LATCH CIRCUIT
DATA CONTROL CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT BUFFER
DQ
Rev. A | Apr. 2012
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Figure3: Simplified State Diagram
IS42/45SM/RM/VM32400G
EXTENDED MODE
REGISTER SET
SELF REFRESH
MODE REGISTER
SET
MRS
IDLE
REF CBR REFRESH
ACT PRE
DEEP POWER DOWN
WRITE
WRITE SUSPEND
CKE ↓ CKE
WRITE
ROW ACTIVE
C.