IS42VS16100E

IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM PRELIMINARY INFORMATION FEBRUARY 2011 FEATURES Clock frequency: 133, 100, 83 MHz Fully synchronous; all signals referenced to a positive clock edge Two banks can be operated simultaneously and independently Dual internal bank controlled by A11 (bank select) Single 1.8V power supply LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave 2048 refresh cycles every 32 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Byte controlled by LDQM and UDQM Package 400-mil 50-pin TSOP II and 60-ball BGA Lead-free package option Auto refresh and self-refresh modes Power down and deep power down PIN DESCRIPTIONS A0-A11 Address Input A0-A10 Row Address Input A11 Bank Select Address A0-A7 Column Address Input DQ0 to DQ15 Data DQ CLK System Clock Input CKE Clock Enable CS Chip Select DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS42VS16100E is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP (Type...