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M93C76-W Dataheets PDF



Part Number M93C76-W
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description EEPROM
Datasheet M93C76-W DatasheetM93C76-W Datasheet (PDF)

M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Datasheet 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM SO8N (150 mil width) TSSOP8 (169 mil width) UFDFPN8 (DFN8) (2 x 3 mm) Product status link M93C46-W M93C56-W M93C56-R M93C66-W M93C66-R M93C76-W M93C76-R M93C86-W M93C86-R Features • Industry standard MICROWIRE™ bus • Single supply voltage: – 2.5 V to 5.5 V for M93Cx6-W – 1.8 V to 5.5 V for M93Cx6-R • Dual organization: by word (x16) or byte (x.

  M93C76-W   M93C76-W


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M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Datasheet 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM SO8N (150 mil width) TSSOP8 (169 mil width) UFDFPN8 (DFN8) (2 x 3 mm) Product status link M93C46-W M93C56-W M93C56-R M93C66-W M93C66-R M93C76-W M93C76-R M93C86-W M93C86-R Features • Industry standard MICROWIRE™ bus • Single supply voltage: – 2.5 V to 5.5 V for M93Cx6-W – 1.8 V to 5.5 V for M93Cx6-R • Dual organization: by word (x16) or byte (x8) • Programming instructions that work on: byte, word or entire memory • Self-timed programming cycle with auto-erase: 5 ms • READY/BUSY signal during programming • 2 MHz clock rate • Sequential read operation • Enhanced ESD/latch-up behavior • More than 4 million write cycles • More than 200-year data retention Package • ECOPACK2 (RoHS compliant) and halogen-free packages: – DFN8 – SO8N – TSSOP8 DS1077 - Rev 19 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description 1 Description The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86 (16 Kbit) are electrically erasable programmable memory (EEPROM) devices accessed through the MICROWIRE™ bus protocol. The memory array can be configured either in bytes (x8b) or in words (x16b). The M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V and the M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature range of - 40 ° C / + 85 ° C. Device M93C86 M93C76 M93C66 M93C56 M93C46 Table 1. Memory size versus organization Number of bits 16384 8192 4096 2048 1024 Number of 8-bit bytes 2048 1024 512 256 128 Number of 16-bit words 1024 512 256 128 64 Figure 1. Logic diagram VCC D Q C M93Cx6 S ORG S D Q C ORG VCC VSS Signal name VSS Table 2. Signal names Chip Select Serial Data input Serial Data output Serial Clock Organization Select Supply voltage Function Ground MS69281V1 Direction Input Input Output Input Input - DS1077 - Rev 19 page 2/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description Figure 2. 8-pin package connections (top view) M93Cx6 S1 C2 D3 Q4 8 VCC 7 DU 6 ORG 5 VSS MS69284V1 1. See Section 11 Package information for package dimensions, and how to identify pin-1. 2. DU = Don't use. The DU (do not use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS. DS1077 - Rev 19 page 3/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Connecting to the serial bus 2 Connecting to the serial bus Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus. Only one device is selected at a time, so only one device drives the Serial data output (Q) line at a time, the other devices are high impedance. The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the bus master leaves the S line in the high impedance state. In applications where the bus master can enter a state where all input/outputs are high-impedance at a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance, the C line is pulled low (while the S line is pulled low). This ensures that S and C do not become high at the same time, and the tSLCH requirement is met. The typical value of R is 100 kΩ. Figure 3. Bus master and memory devices on the serial bus R SDO SDI SCK Bus master R CS3 CS2 CS1 C QD VCC VSS M93xxx memory device R S ORG VCC VSS C QD VCC VSS M93xxx memory device R C Q D VCC VSS M93xxx memory device S ORG S ORG AI14377b DS1077 - Rev 19 page 4/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Operating features 3 Operating features 3.1 3.1.1 3.1.2 3.1.3 3.1.4 Supply voltage (VCC) Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float and should be driven to VSS, it is therefore recommended to connect the S line to VSS via a suita.


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