Parallel D Register
54F 74F378 Parallel D Register with Enable
Obsolete
January 1995
54F 74F378 Parallel D Register with Enable
General ...
Description
54F 74F378 Parallel D Register with Enable
Obsolete
January 1995
54F 74F378 Parallel D Register with Enable
General Description
The ’F378 is a 6-bit register with a buffered common Enable This device is similar to the ’F174 but with common Enable rather than common Master Reset
Features
Y 6-bit high-speed parallel register Y Positive edge-triggered D-type inputs Y Fully buffered common clock and enable inputs Y Input clamp diodes limit high-speed termination effects Y Full TTL and CMOS compatible
Commercial 74F378PC
74F378SC (Note 1) 74F378SJ (Note 1)
Military 54F378DM (QB)
54F378FM (QB) 54F378LM (QB)
Package Number N16E J16A M16A M16D W16A E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak
Pin Assignment for LCC
TL F 9526–1
IEEE IEC
TL F 9526 – 2
TL F 9526 – 3
TL F 9526–4
TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9526
RRD-B30M75 Printed in U S A
Obsolete
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L Input IIH IIL HIGH LOW Output IOH IOL
E D0 – D5 CP Q0 – Q5
Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Ed...
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