CDP1877C

CDP1877, CDP1877C March 1997 Programmable Interrupt Controller (PIC) Description The CDP1877 and CDP1877C are programmable 8-level interrupt controllers designed for use in CDP1800 series microprocessor systems. They provide added versatility by extending the number of permissible interrupts from 1 to N in increments of 8. When a high to low transition occurs on any of the PIC interrupt lines (IR0 to IR7), it will be latched and, unless the request is masked, it will cause the INTERRUPT line on the PIC and consequently the INTERRUPT input on the CPU to go low. The CPU accesses the PIC by having interrupt vector register R(1) loaded with the memory address of the PIC. After the interrupt S3 cycle, this register value will appear at the CPU address bus, causing the CPU to fetch an instruction from the PIC. This fetch cycle clears the interrupt request latch bit to accept a new high-to-low transition, and also causes the PIC to issue a long branch instruction (CO) followed by the preprogrammed vector address written into the PIC’s address registers, causing the CPU to branch to the address corresponding to the highest priority active interrupt request. If no other unmasked interrupts are pending, the INTERRUPT output of the PIC will return high. When an interrupt is requested on a masked interrupt line, it will be latched but it will not cause the PIC INTERRUPT output to go low. All pending interrupts, masked and unmasked, will be indicated by a “1” in the corresponding bit of ...