Document
®
Data Sheet
CDP68HC68A2
April 2002
FN1963.4
CMOS Serial 10-Bit A/D Converter
The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive approximation analog to digital converter (A/D) with a standard Serial Peripheral Interface (SPI) bus and eight multiplexed analog inputs. Voltage referencing is user selectable to be relative to either VDD or analog channel 0 (AI0). The analog inputs can range between VSS and VDD.
The CDP68HC68A2 employs a switched capacitor, successive approximation A/D conversion technique which provides an inherent sample-and-hold function. An onchip Schmitt oscillator provides the internal timing for the A/D converter. The Schmitt input can be externally clocked or connected to a single, external capacitor to form an RC oscillator with a period of approximately 10-30ns per picofarad.
Conversion times are proportional to the oscillator period. At the maximum specified frequency of 1MHz, 10-bit conversions take 14μs per channel. At the same frequency, 8-bit conversions consume 12μs per channel.
The versatile modes of the CDP68HC68A2 allow any combination of the eight input channels to be enabled and any one of the selected channels to be specified as the “starting” channel. Conversions proceed sequentially beginning with the starting channel. Nonselected channels are skipped. Modes can be selected to: sequence from channel to channel on command; sequence through channels automatically, converting each channel one time; or sequence repeatedly through all channels.
The results of 10-bit conversions are stored in 8-bit register pairs (one pair per channel). The two most significant bits are stored in the first register of each pair and the eight least significant bits are stored in the second register of the pair. To allow faster access, in the 8-bit mode, the results of conversions are stored in a single register per channel.
A read-only STATUS register facilitates monitoring the status of conversions. The STATUS register can simply be polled or the INT pin can be enabled for interrupt driven communications.
Ordering Information
TEMP. RANGE
PART NUMBER
(oC)
PACKAGE
CDP68HC68A2E
-40 to 85 16 Ld PDIP
CDP68HC68A2M
-40 to 85 20 Ld SOIC
CDP68HC68A2M96 -40 to 85 Tape & Reel
PKG. NO.
E16.3
M20.3
M20.3
Features
• 10-Bit Resolution • 8-Bit Mode for Single Data Byte Transfers • SPI (Serial Peripheral Interface) Compatible • Operates Ratiometrically Referencing VDD or an External
Source • 14μs 10-Bit Conversion Time • 8 Multiplexed Analog Input Channels • Independent Channel Select • Three Modes of Operation • On Chip Oscillator • Low Power CMOS Circuitry • Intrinsic Sample and Hold
Pinouts
CDP68HC68A2E (PDIP) TOP VIEW
OSC 1 INT 2
MISO 3 MOSI 4 SCK 5
CE 6 AI0 / EXT. REF 7
VSS 8
16 VDD 15 AI1 14 AI2 13 AI3 12 AI4 11 AI5 10 AI6 9 AI7
CDP68HC68A2M (SOIC) TOP VIEW
OSC 1 INT 2
MISO 3 MOSI 4
NC 5 NC 6 SCK 7 CE 8 AI0 / EXT. REF 9 VSS 10
20 VDD 19 AI1 18 AI2 17 AI3 16 NC 15 NC 14 AI4 13 AI5 12 AI6 11 AI7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Block Diagram
CDP68HC68A2
ACC LATCH COMPARATOR
3
STATUS REGISTER
SPI CONTROL LOGIC
8
MOSI
SCK
8 MISO
CE CONTROL LOGIC
CONTROL REGISTER 4
4
4
ADDRESS CONTROL LOGIC
CAR
CHOPPER STABILIZED COMPARATOR
4
66
ADDRESS REGISTER
3
STATUS CONTROL REGISTERS REGISTERS
3
SHIFT REGISTER 8
DATA REGISTERS (READ ONLY) 8
A/D CONVERTER LATCH 10
SUCCESSIVE APPROXIMATION CONTROL LOGIC
10-BIT CAPACITOR ARRAY CAPACITOR SWITCH ARRAY
ANALOG MULTIPLEXER 8
ANALOG INPUTS
INTERRUPT LOGIC
INT
OSCILLATOR 12
OSC
REFERENCE
VSS
VDD
AI0*
AI7
NOTE: USED AS VOLTAGE INPUT IN EXTERNAL REFERENCE MODE.
2
CDP68HC68A2
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V (Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Conditions (Note 1)
Temperature Ambient, TA . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC DC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Min, 6V Max
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Power Dissipation Per Package
TA TA
= =
-40oC to 60oC (Package Type E) 60oC to 85oC (Package Type E)
.
Derate Linearly at. . . . . . . . . . . . . . . .
(PD) ............ . . . 12mW/oC
.. to
500mW 200mW
TA TA
= =
-40oC -70oC
to to
70oC 85oC
(Package (Package
Derate Linearly at. . . . . . . .
Type M) Type M) .......
(Note 3) . . . . . . (Note 3) . . . . 6.