DatasheetsPDF.com

SS542 Dataheets PDF



Part Number SS542
Manufacturers SEC
Logo SEC
Description Hall Latch - High Sensitivity
Datasheet SS542 DatasheetSS542 Datasheet (PDF)

SS542 Hall Latch - High Sensitivity Features and Benefits – CMOS Hall IC Technology – Bipolar Output CMOS Multi-purpose latch – Solid-State Reliability much better than reed switch – Operation down to 2.5V – Supply current down to 45μA, very low power consumption – CMOS inverter output (no pull-up resistance) – High sensitivity for direct reed switch re- placement application Application Examples – Solid state switch – Magneto-electric conversion switch – Magnet proximity sensor for reed switc.

  SS542   SS542


Document
SS542 Hall Latch - High Sensitivity Features and Benefits – CMOS Hall IC Technology – Bipolar Output CMOS Multi-purpose latch – Solid-State Reliability much better than reed switch – Operation down to 2.5V – Supply current down to 45μA, very low power consumption – CMOS inverter output (no pull-up resistance) – High sensitivity for direct reed switch re- placement application Application Examples – Solid state switch – Magneto-electric conversion switch – Magnet proximity sensor for reed switch re- placement in low duty cycle applications 3 pin TSOT23 (suffix ST) 3 pin SIP (suffix UA) Functional Block Diagram 1 V3.10 Nov 1, 2013 SS542 Hall Latch - High Sensitivity General Description The SS542 Hall effect sensor IC is fabricated from mixed signal CMOS technology. It incorporates advanced chopper-stabilization techniques to provide accurate and stable magnetic switch points. The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and analog signal processing circuits. This serves to place the high current-consuming portions of the circuit into a “Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall element is evaluated against the predefined thresholds. If the flux density is above or below the Bop/Brp thresholds then the output transistor is driven to change states accordingly. While in the “Sleep” cycle the output transistor is latched in its previous state. The design has been optimized for service in applications requiring extended operating lifetime in battery powered systems. The output transistor of the SS542 switches low (turns on) when a magnetic field perpendicular to the Hall sensor exceeds the operate point threshold (BOP). After turn-on, the output voltage is VDS. The device remains on if the south pole is removed (B→0). Thi s latching property defines the device as a magnetic memory. When the magnetic field is reduced below the release point, BRP, the Output transistor turns off (goes high). The difference in the magnetic operate and release points is the hysteresis (BHYS) of the device. This built-in hysteresis prevents output oscillation near the switching point, and allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. The TSOT-23 device is reversed from the UA package. The TSOT-23 output transistor will be latched on in the presence of a sufficiently strong North pole magnetic field applied to the marked face. Glossary of Terms Output level Output level OUT = High OUT = High BHYS BHYS BRP -30Gs typ OUT = Low 0mT BOP 30Gs typ Flux density UA package - Latch characteristic OUT = Low BRP -30Gs typ 0mT BOP 30Gs typ Flux density STT package - Latch characteristic Internal Timing Circuit Current Iaw Period Iav Isp 0 Awake Taw:20μs Sleep Tsl:600μs Sample & Output Time 2 V3.10 Nov 1, 2013 Absolute Maximum Ratings Parameter Supply Voltage Supply Current Output Voltage Output Current Operating Temperature Range Storage Temperature Rang ESD Sensitivity Symbol VDD IDD VOUT IOUT TA TS - Value 28 50 28 50 -40 to 85 -50 to 150 4000 SS542 Hall Latch - High Sensitivity Units V mA V mA °C °C V Operating Temperature Range Symbol Value Units Temperature Suffix “ E” TA -40 to 85 °C Temperature Suffix “ K” Temperature Suffix “ L” TA -40 to 125 °C TA -40 to 150 °C Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum- rated conditions for ex- tended periods may affect device reliability. General Electrical Specifications DC Operating Parameters TA = 25°C, VDD= 2.5V to 5.5V (unless otherwise specified) Parameter Symbol Test Conditions Min Operating voltage VDD Operating 2.5 Supply current IDD Average Output Current Saturation Voltage Awake mode time Sleep mode time IOUT VSAT TAW TSL IOUT=1mA Operating Operating Typ 3 45 1.0 20 Max 5.5 0.4 600 Units V μA mA V μS μS Magnetic Specifications DC Operating Parameters VDD = 2.5 to 5.5V (unless otherwise specified) Package Parameter Symbol Test Conditions Operating Point BOP Ta=25°C UA Release Point BRP Vdd=2.75V DC Hysteresis BHYST Operating Point BOP Ta=25°C SO Release Point BRP Vdd=2.75V DC Hysteresis BHYST 3 Min Typ Max Units 5 25 40 G -40 -25 -5 G 40 G -40 -25 -5 G 5 25 40 G 40 G V3.10 Nov 1, 2013 SS542 Hall Latch - High Sensitivity Output Behavior versus Magnetic Pole DC Operating Parameters TA = -40°C to 150°C, VDD = 2.5 to 5.5V (unless otherwise specified) Test Conditions (UA) Test Conditions (SO) OUT B < BRP B > BRP High B > BOP B < BOP Low The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be turned on(drops low) in the presence of a sufficiently strong North pole magnetic field applied to the marked face and turned off(hoists high) in the presence of a sufficiently strong South pole magnetic field. 4 V3.10 N.


SS2712 SS542 SS579


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)