SAA7715H

INTEGRATED CIRCUITS DATA SHEET SAA7715H Digital Signal Processor Preliminary specification File under Integrated Circuits, IC01 2001 May 07 Philips Semiconductors Digital Signal Processor Preliminary specification SAA7715H CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 FEATURES Hardware Possible firmware APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION PLL division factors for different clock inputs The word select PLL The Filter Stream DAC (FSDAC) Interpolation filter Noise shaper Function of pin POM Power off plop suppression Pin VREFDA for internal reference Supply of the analog outputs External control pins Digital serial inputs/outputs and SPDIF inputs Digital serial inputs/outputs SPDIF inputs I2C-bus interface (pins SCL and SDA) Reset Power-down mode Power supply connection and EMC Test mode connections (pins TSCAN, RTCB and SHTCB) I2C-BUS PROTOCOL Addressing Slave address (pin A0) Write cycles Read cycles Program RAM Data word alignment I2C-bus memory map specification I2C-bus memory map definition Table definitions 10 10.1 10.1.1 10.2 10.2.1 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.4 10.4.1 10.4.2 10.4.3 10.4.4 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 SOFTWARE IN ROM DESCRIPTION Audio dynamics compressor Theory of operation Audio enhancer Theor...