HD74LS73A

HD74LS73A Dual J-K Flip-Flops (with Clear) Features Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS73AP DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS73ARPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. Pin Arrangement REJ03D0414–0300 Rev.3.00 Jul.22.2005 Taping Abbreviation (Quantity) — EL (2,500 pcs/reel) 1CK 1 1CLR 2 1K 3 VCC 2CK 4 5 2CLR 6 2J 7 CLR JQ CK KQ KQ CK JQ CLR (Top view) 14 1J 13 1Q 12 1Q 11 GND 10 2K 9 2Q 8 2Q Function Table Inputs Outputs Clear Clock J K QQ L XX X LH H ↓ L L Q0 Q0 H↓H L HL H↓ LHLH H↓HH Toggle H H X X QO H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. QO Rev.3.00, Jul.22.2005, page 1 of 6 HD74LS73A Block Diagram (1/2) QQ Clear KJ Clock Absolute Maximum Ratings Item Symbol Ratings Supply voltage VCC 7 Input voltage VIN 7 Power dissipation PT 400 Storage temperature Tstg –65 to +150 Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Supply voltage VCC O...