L4984D
Application information
Figure 26. Linemodulated fixedofftime modulator: a) internal block diagram; b) key
waveforms
TIMER
MULT
COMP
MULT
0
Multiplier
CS
PWM
+ Comparator

TOFF
S
TON
R
t
t
TIMER
ITimer
CT

+
ON
OFF
SQ
R
PWM Latch
Driver
GD
Q
GD
CS
Multiplier output
t
t
t
t
a) b)
AM13242v1
With reference to the schematic and the relevant key waveforms in Figure 26, an offtime
proportional to the instantaneous line voltage is achieved by charging the capacitor CT with
a constant current ITIMER, accurately fixed internally and temperature compensated, while
the MOSFET is off and commanding MOSFET turnon (and resetting CT at zero) as the
voltage across CT equals that on the MULT pin. The voltage on this pin is:
Equation 5
VMULT = KP Vpk sin θ
where KP is the divider ratio of the resistors biasing the MULT pin. As a result:
Equation 6
TOFF
=
CT
ITIMER
KP
Vpk sinθ
→
Kt
=
CT
ITIMER
KP
and the switching frequency is:
Equation 7
fsw
=1
Tsw
= ITIMER
KP CT Vout
=1
K t Vout
The timing capacitor CT, therefore, is selected with the following design formula:
Equation 8
CT
=
ITIMER
KP Vout fsw
Vout and fsw are design specifications, KP is chosen so that the voltage on the MULT pin is
within the multiplier linearity range (0 to 3 V) and ITIMER is specified in Section 3: Electrical
characteristics.
DocID024474 Rev 1
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