CGS702V

CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI September 1995 CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI General Description The CGS702 is an off-the-shelf clock driver specifically designed for today’s high speed processors It provides low skew outputs which are produced at different frequencies from three fixed input references The CGS702 is a reduced EMI version of the CGS700 The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz 33 MHz or 40 MHz The PLL using a charge pump and an internal loop filter multiplies this input frequency to create a maximum output frequency of four times the input The device includes a TRI-STATE control pin to disable the outputs while the PLL is still in lock This function allows testing the board without having to wait to acquire the lock once the testing is complete (Continued) Y Y Y Y Y Y Y Y Y Y Y Y Y Features Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL and TOSLH) on 1x outputs PentiumTM and PowerPCTM compatible Output buffer of nine drivers for large fanout 25 MHz – 160 MHz output frequency range Outputs operating at 4x 2x 1x of the reference frequency for multi-frequency bus applications Selectable output frequency Internal loop filter to reduce noise and jitter Separate Analog and digital VCC and Ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output c...