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EDI88512CA Dataheets PDF



Part Number EDI88512CA
Manufacturers Microsemi
Logo Microsemi
Description 512Kx8 Monolithic SRAM
Datasheet EDI88512CA DatasheetEDI88512CA Datasheet (PDF)

EDI88512CA 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES  Access Times of 15, 17, 20, 25, 35, 45, 55ns  Data Retention Function (LPA version)  TTL Compatible Inputs and Outputs  Fully Static, No Clocks  Organized as 512Kx8  Commercial, Industrial and Military Temperature Ranges  32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Pa.

  EDI88512CA   EDI88512CA



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EDI88512CA 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES  Access Times of 15, 17, 20, 25, 35, 45, 55ns  Data Retention Function (LPA version)  TTL Compatible Inputs and Outputs  Fully Static, No Clocks  Organized as 512Kx8  Commercial, Industrial and Military Temperature Ranges  32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 321) • Ceramic SOJ (Package 140)  36 lead JEDEC Approved Revolutionary Pinout • Ceramic Flatpack (Package 316) • Ceramic SOJ (Package 327) • Ceramic LCC (Package 502)  Single +5V (±10%) Supply Operation The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535. *This product is subject to change without notice. FIGURE 1 – PIN CONFIGURATION 36 PIN TOP VIEW A0 1 36 NC A1 2 35 A18 A2 3 34 A17 A3 4 33 A16 A4 5 32 A15 CS# 6 31 OE# I/O0 7 30 I/O7 I/O1 8 Vcc 9 Vss 10 36 pin Revolutionary 29 28 27 I/O6 Vss Vcc I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE# 13 24 A14 A5 14 23 A13 A6 15 22 A12 A7 16 21 A11 A8 17 20 A10 A9 18 19 NC 32 PIN TOP VIEW A18 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 Vss 16 32 pin Evolutionary 32 Vcc 31 A15 30 A17 29 WE# 28 A13 27 A8 26 A9 25 A11 24 OE# 23 A10 22 CS# 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 I/O0-7 A0-18 WE# CS# OE# VCC VSS NC PIN DESCRIPTION Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected BLOCK DIAGRAM Memory Array A0-18 WE# CS# OE# Address Buffer Address Decoder I/O Circuits I/O0-7 Microsemi Corporation reserves the right to change products or specifications without notice. May 2014 © 2014 Microsemi Corporation. All rights reserved. Rev. 15 1 Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp EDI88512CA ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Voltage on any pin relative to Vss -0.5 to 7.0 V Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation 0  TA  +70 -40  TA  +85 -55  TA  +125 -65  TA +150 1.5 °C °C °C °C W Output Current 20 mA Junction Temperature, TJ 175 °C NOTE: Stress greater than those listed u.


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