Document
PI6C49004
Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage • Uses 25MHz xtal such as Saronix-eCera™ SRX7278 • Twelve PCIe® 100MHz outputs with optional -0.5% spread
spectrum support • Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining • One frequency selectable 33/66/133MHz LVCMOS output • One 32.256MHz LVCMOS output • Industrial temperature -40°C to 85°C • Package: 56-pin TSSOP package
Description
The PI6C49004 is a clock generator device intended for PCIe®/ networking applications. The device includes twelve 100MHz differential Host Clock Signal Level (HCSL) outputs for PCIe, two single-ended 50MHz outputs, one single-ended 32.256MHz output, and one selectable single-ended 33/66/133MHz output.
Using a serially programmable SMBUS interface, the PI6C49004 incorporates spread spectrum modulation on the twelve 100MHz HCSL PCIe outputs, and independent frequency margining on the 50MHz output, 33.3333MHz and 66.6666MHz clock outputs.
Pin Configuration
Block Diagram
25 MHz crystal or clock input
Clock Buffer/ Crystal Oscillator
VDD 12
SCLK SDATA PD_RESET
PLL, Dividers, Buffers, and Logic
12 100M_OUT(0-11)
2 50M_OUT(1-2)
33/66/133M_OUT1
32.256M_OUT1
8 GND
ISET 475 Ohms 1%
VDD IREF
NC 100M_Q11100M_Q11+ 100M_Q10100M_Q10+
VDD VDD GND 100M_Q9100M_Q9+ 100M_Q8100M_Q8+ 100M_Q7100M_Q7+ SCLK SDATA GND 50M_OUT1 50M_OUT2 VDD GND VDD 32.256M_OUT1 GND
NC PD_RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
11-0080
09-0098
1
56 GND 55 VDD 54 100M_Q053 100M_Q0+ 52 100M_Q1+ 51 100M_Q150 VDD 49 GND 48 VDD 47 100M_Q2+ 46 100M_Q245 100M_Q3+ 44 100M_Q343 100M_Q4+ 42 100M_Q441 100M_Q5+ 40 100M_Q539 VDD 38 GND 37 VDD 36 100M_Q6+ 35 100M_Q634 33/66/133M_OUT1 33 VDD 32 GND 31 VDD 30 X2 29 X1
PS9047A
04/11/11
Pin Description
Pin # Pin Name 1 VDD 2 IREF 3 NC 4 100M_Q115 100M_Q11+ 6 100M_Q107 100M_Q10+ 8 VDD 9 VDD 10 GND 11 100M_Q912 100M_Q9+ 13 100M_Q814 100M_Q8+ 15 100M_Q716 100M_Q7+ 17 SCLK 18 SDATA 19 GND
20 50M_Out1
Pin Type Power Output
Output Output Output Output Power Power Power Output Output Output Output Output Output Input I/O Power
Output
21 50M_Out2
Output
22 VDD 23 GND 24 VDD
Power Power Power
25 32.256M_Out1 Output
26 GND
Power
27 NC
28 PD_RESET
Input
29 X1 30 X2 31 VDD 32 GND 33 VDD
Input Output Power Power Power
34 33/66/133M_Out1 Output
35 100M_Q6(Continued)
Output
PI6C49004 Networking Clock Generator
Pin Description 3.3V Supply Pin Connect to 475-Ohm resistor to set HCSL output drive current No connect. Leave open 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 3.3V Supply Pin 3.3V Supply Pin Ground 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output SMBus compatible input clock. Supports fast mode 400kHz input clock. SMBus compatible data line Ground 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down. 50MHz LVCMOS output. Wh.