PI6CDBL402B

PI6CDBL402B 4 -Output Low Power PCIE GEN 1-2-3 Buffer Features ÎÎPhase jitter filter for PCIe 3.0/ 2.0/ 1.0 application ÎÎLow power consumption with independent output power supply 1.8V~3.3V ÎÎLow skew < 60ps ÎÎLow cycle-to-cycle jitter - 45ps (typ.) @100MHz ÎÎ< 1 ps additive RMS phase jitter ÎÎOutput Enable for all outputs ÎÎProgrammable PLL Bandwidth ÎÎ100 MHz PLL Mode operation ÎÎ1 - 400 MHz Bypass Mode operation ÎÎ3.3V Operation ÎÎPackaging (Pb-free and Green): -28-Pin TSSOP (L28) Block Diagram Description Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification. The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of PWRDWN# and SMBus, SCLK and SDA. Pin Configuration OE_INV OE_0 & OE_3 PWRDWN# Output Control SCLK SDA PLL/BYPASS# SRC SRC# SMBus Controller PLL_BW# PLL OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# VDD SRC SRC# GND VDDO OUT0 OUT0# OE_0 OUT1 OUT1# VDDO PPLLLL/B/BYYPPAASSSS# SCLK SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VDD_A 27 GNDA 26 NC 25 OE_INV 24 VDDO 23 OUT3 22 OUT3# 21 OE_3 20 OUT2 19 OUT2# 18 VDDO 17 PLL_BW# 16 VDD 15 PWRDWN# All trademarks are property of their respective owners. 15-0083 1 www.pericom.com 06/30/15 PI6CDBL40...