UT54ACS74

Standard Products UT54ACS74/UT54ACTS74 Dual D Flip-Flops with Clear & Preset Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS74 - SMD 5962-96534 ‰ UT54ACTS74 - SMD 5962-96535 DESCRIPTION The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE PRE L H L H H H INPUTS CLR CLK HX LX LX H↑ H↑ HL OUTPUT D QQ XHL X LH X H1 H1 HHL L LH X Qo Qo Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. PINOUTS 14-Pin DIP Top View CLR1 D1 CLK1 PRE1 Q1 Q1 VSS 1 14 2 13 3 12 4 11 5 10 69 78 VDD CLR2 D2 CLK2 PRE2 Q2 ...