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UT54ACS163 Dataheets PDF



Part Number UT54ACS163
Manufacturers Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology
Description 4-Bit Synchronous Counters
Datasheet UT54ACS163 DatasheetUT54ACS163 Datasheet (PDF)

Standard Products UT54ACS163/UT54ACTS163 4-Bit Synchronous Counters Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ Internal look-ahead for fast counting ‰ Carry output for n-bit cascading ‰ Synchronous counting ‰ Synchronously programmable ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 16-pin DIP - 16-lead flatpack ‰ UT54ACS163 - SMD 5962-96554 ‰ UT54ACTS163 - SMD 5962-96555 DESCRIPTION Th.

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Standard Products UT54ACS163/UT54ACTS163 4-Bit Synchronous Counters Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ Internal look-ahead for fast counting ‰ Carry output for n-bit cascading ‰ Synchronous counting ‰ Synchronously programmable ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 16-pin DIP - 16-lead flatpack ‰ UT54ACS163 - SMD 5962-96554 ‰ UT54ACTS163 - SMD 5962-96555 DESCRIPTION The UT54ACS163 and the UT54ACTS163 are synchronous presettable 4-bit binary counters that feature internal carry lookahead logic for high-speed counting designs. Synchronous operation occurs by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. The counters are fully programmable (i.e., they may be preset to any number between 0 and 15). Presetting is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the load data after the next clock pulse. The clear function is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse. This synchronous clear allows the count length to be modified by decoding the Q outputs for the maximum count desired. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55°C to +125°C. PINOUTS 16-Pin DIP Top View CLR CLK A B C D ENP VSS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 VDD RCO QA QB QC QD ENT LOAD CLR CLK A B C D ENP VSS 16-Lead Flatpack Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 VDD RCO QA QB QC QD ENT LOAD LOGIC SYMBOL (1) CLR (9) LOAD ENT ENP CLK (10) (7) (2) CTRDIV 16 5CT=0 M1 M2 3CT = 15 G3 G4 C5/2,3,4+ (3) A (4) B (5) C (6) D 1,5D (1) (2) (4) (8) (15) RCO (14) QA (13) QB (12) QC (11) QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 FUNCTION TABLE Operating Mode CLR Reset (Clear) Parallel Load Count Inhibit l h3 h3 h3 h3 h3 CLK ↑ ↑ ↑ ↑ X X ENP X X X h l2 X ENT X X X h X l2 LOAD X l l h h3 h3 DATA A,B,C,D X l h X X X H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition Notes: 1. The RCO output is high when ENT is high and the counter is at terminal count HHHH. 2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations. 3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations. LOGIC DIAGRAM QN RCO LL LL H1 Count 1 QN 1 QN L (2) CLK CLR (1) LOAD (9) ENP (7) (10) ENT (3) DATA A (4) DATA B DQ C Q (14) QA DQ C Q (13) QB (5) DATA C DQ C Q (12) QC (6) DATA D DQ C Q (11) QD (15) RCO 2 OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 0.3 to 7.0 V VI/O TSTG TJ TLS ΘJC II Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current -.3 to VDD +.3 -65 to +150 +175 +300 20 ±10 V °C °C °C °C/W mA PD Maximum power dissipation 1W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V °C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Ptotal PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACT.


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