UT54ACS165E

UT54ACS165E 8-Bit Parallel Shift Registers October 2008 www.aeroflex.com/Logic FEATURES Complementary outputs Direct overriding load (data) inputs Gated clock inputs Parallel-to-serial data conversions 0.6μm CRH CMOS Process - Latchup immune High speed Low power consumption Wide operating power supply from 3.0V to 5.5V Available QML Q or V processes 16-lead flatpack DESCRIPTION The UT54ACS165E is an 8-bit serial shift register that, when clocked, shifts the data toward serial output QH. Parallel-in access to each stage is provided by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output QH . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs. The device is characterized over the full HiRel temperature range of -55°C to +125°C. PINOUT SH/LD CLK E F G H QH VSS 16-Lead Flatpack Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 VDD CLK INH D C B A SER QH FUNCTION TABL...