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GS4915 Dataheets PDF



Part Number GS4915
Manufacturers Gennum
Logo Gennum
Description ClockCleaner
Datasheet GS4915 DatasheetGS4915 Datasheet (PDF)

GS4915 ClockCleaner™ Key Features • Reduces jitter for clocks of 148.5MHz, 148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz and 27MHz • Output jitter as low as 20ps peak to peak • Automatic bypass mode for all other clock rates • Loop bandwidth adjustable as low as 2kHz • Output skew control • Input selectable as differential or single-ended • Both single-ended and differential outputs • Uses the GO1555 VCO • Small 6mm x 6mm 40-pin QFN package • Pb-free and RoHS compliant Applications High definition vi.

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GS4915 ClockCleaner™ Key Features • Reduces jitter for clocks of 148.5MHz, 148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz and 27MHz • Output jitter as low as 20ps peak to peak • Automatic bypass mode for all other clock rates • Loop bandwidth adjustable as low as 2kHz • Output skew control • Input selectable as differential or single-ended • Both single-ended and differential outputs • Uses the GO1555 VCO • Small 6mm x 6mm 40-pin QFN package • Pb-free and RoHS compliant Applications High definition video systems. Digital video recording, playback, processing and display devices. Description The GS4915 provides a low jitter clock output when fed with an HD or SD video clock input. Other input clock frequencies between 12MHz and 165MHz can be automatically passed through to the GS4915 outputs. An internal 2:1 mux allows the user to select between a differential or single-ended (LVCMOS) input clock. Both a single-ended LVCMOS- compatible and an LVDS-compatible differential output are provided. The GS4915 may operate in either auto or fixed frequency mode. In auto mode, the device will automatically clean the selected input clock if its frequency is found to be one of the supported SD or HD clock rates. In fixed mode, the user selects only one of these frequencies to be cleaned. In addition, the device allows the user to select between auto or manual bypass operation. In autobypass mode, the GS4915 will automatically bypass its cleaning stage and pass the input clock signal directly to the output whenever the device is unlocked, which includes the case where the input frequency is something other than the five frequencies supported. In manual bypass mode, the input signal passes through directly to the output. The GS4915 can optionally double the output frequency for 74.25MHz or 74.175MHz HD clocks in order to provide optimal jitter performance of some serializers. The GS4915 also provides the user with a 2-state skew control. The output clocks produced by the device may be advanced by ¼ of an output CLK period in order to accommodate downstream setup and hold requirements. The GS4915 is designed to operate with the GO1555 VCO. The GS4915 Clock Cleaner complements Gennum's GS4911B Clock and Timing Generator for implementing a video genlock solution. Whereas the GS4911B itself cleans low-frequency jitter, the GS4915 is designed to clean primarily the higher frequency jitter of clocks generated by the GS4911B. GS4915 ClockCleaner™ Data Sheet 39145 - 5 June 2009 www.gennum.com 1 of 27 Functional Block Diagram REG_VDD VCO_VDD CP_VDD LF CP_RES VCO VCO CLKIN CLKIN CLKIN_SE DIFF I/P Buffer S-E I/P Buffer 0 1 IPSEL 2.5V Regulator VCO Receiver Phase Detector Charge Pump Divide by N Clock Cleaning PLL Skew Select clkout clkin 0 1 Frequency Detection Digital Control Block bypass DIFF O/P Buffer CLKOUT CLKOUT S-E O/P Buffer CLKOUT_SE LOCK RESET SKEW_EN BYPASS AUTOBYPASS FCTRL[1:0] DOUBLE GS4915 Functional Block Diagram GS4915 ClockCleaner™ Data Sheet 39145 - 5 June 2009 2 of 27 Revision History Version 5 4 3 2 1 0 ECR 151935 149060 146729 145306 144087 142746 PCN Date Changes and/or Modifications – June 2009 Updated document with new template. – February 2008 Updated Figure 4-1: GS4915 Typical Application Circuit. – November Converted document to Data Sheet. 2007 Updated Power Consumption values in Table 2-1: DC Electrical Characteristics. – August 2007 Defined IO_VDD see Note 5 in 2.2 DC Electrical Characteristics and added chamfer dimensions in 6.3 Recommended PCB Footprint. Added pin descriptions for D-VDD, IN_VDD and SEto 1.2 Pin Descriptions. Changed Loop Bandwidth to 2kHz in Key Features. Added section 3.3.3 Loop Filter and Table 3-1: Loop Filter Component Values. Changed some pin descriptions. Updated power consumption values in Table 2-1: DC Electrical Characteristics. 43245 February 2007 Corrected pin 38 (CP_VDD) connection on Typical Application Circuit. – November Modified Table 1-1: Pin Descriptions. 2006 Updated DC Electrical Characteristics and AC Electrical Characteristics table. Modified Typical Application Circuit. Added junction - board thermal resistance parameter to section 6.4 Packaging Data. GS4915 ClockCleaner™ Data Sheet 39145 - 5 June 2009 3 of 27 Contents Key Features ........................................................................................................................................................1 Applications ......................................................................................................................................................... 1 Description ........................................................................................................................................................... 1 Functional Block Diagram ..............................................................................................................................2 Revision History .......................


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