Document
GS4901B/GS4900B SD Clock and Timing Generator with GENLOCK
Key Features
Video Clock Synthesis • Pre-programmed for 4 video clock periods (14.32 MHz, 27
MHz, 36 MHz, and 54 MHz) • Accuracy of free-running clock frequency limited only by
crystal reference • One differential and two single-ended video clock outputs • Each clock may be individually delayed for skew control • Video output clock may be directly connected to Gennum’s
serializers for a SMPTE-compliant SDI output
Audio Clock Synthesis (GS4901B only) • Three audio clock outputs • Generates any audio clock up to 512*96kHz • Pre-programmed for 7 audio clocks
Timing Generation • Generates up to 8 timing signals at a time • Choose from 9 pre-programmed timing signals: H and V sync
and blanking, F Sync, F Digital, AFS (GS4901B only), Display Enable, 10FID, and up to 4 user-defined timing signals • Pre-programmed to generate timing for 9 different video formats
Genlock Capability • Clocks may be free-running or genlocked to an input
reference with a variable offset step size of 100-200ps (depending on exact clock frequency) • Variable timing offset step size of 100-200ps up to one frame • Output may be cross-locked to a different input reference • Freeze operation on loss of reference • Optional crash or drift lock on application of reference • Automatic input format detection
General Features • Reduces design complexity and saves board space - 9mm x
9mm package plus crystal reference replaces multiple VCXOs, PLLs and timing generators • Pb-free and RoHS Compliant • Low power operation typically 300mW • 1.8V core and 1.8V or 3.3V I/O power supplies • 64-PIN QFN package
Applications
• Video cameras; Digital audio and/or video recording/play back devices; Digital audio and/or video processing devices; Computer/video displays; DVD/MPEG devices; Digital Set top boxes; Video projectors; High definition video systems; Multi-media PC applications
Description
The GS4901B is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. It can be used to generate video and audio clocks and timing signals, and allows multiple devices to be genlocked to an input reference.
The GS4900B includes all the features of the GS4901B, but does not offer audio clocks or AFS pulse generation.
The GS4901B/GS4900B will recognize input reference signals conforming to 36 different video standards, and will genlock the output timing information to the incoming reference. The GS4901B/GS4900B supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected.
The user may select to output one of 4 different video sample clock rates. The chosen clock frequency can be further divided using internal dividers, and is available on two video clock outputs and one LVDS video clock output pair. The video clocks are frequency and phased-locked to the horizontal timing reference, and can be individually delayed with respect to the timing outputs for clock skew control.
Eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 9 different video formats: HSync, Hblanking, VSync, Vblanking, F sync, F digital, AFS (GS4901B only), DE, and 10FID. These timing outputs may be locked to the input reference signal for genlock timing and may be phase adjusted via internal registers.
In addition, the GS4901B provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7kHz to 96kHz. Audio to video phasing is accomplished by an external 10FID input reference, a 10FID signal specified via internal registers, or a user-programmed audio frame sequence.
The GS4901B/GS4900B is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant).
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
www.gennum.com
1 of 102
X1 X2 ASR_SEL[2:0] VID_STD[5:0] GENLOCK LOCK_LOST
REF_LOST
HSYNC VSYNC FSYNC 10FID
27MHz Input Reference Rate Identification
and Control ref_rate
Clock Synthesis and Control
Flywheel and Video Timing Generator
Clock Phase Adjust
pclk
aclk_512 aclk_384
user[4:1]
AFS 10FID DE F digital F sync V blanking
V sync
H blanking H sync
Crosspoint
Video Clock Divide
3x Video Clock Delay Adjust
Audio Clock Divide
TIMING_OUT_8 TIMING_OUT_7 TIMING_OUT_6 TIMING_OUT_5 TIMING_OUT_4 TIMING_OUT_3 TIMING_OUT_2 TIMING_OUT_1
PCLK1 PCLK2 PCLK3 PCLK3
ACLK1 ACLK2 ACLK3
Application Programming Interace
JTAG/HOST SCLK_TCLK
SDIN_TDI SDOUT_TDO
CS_TMS
GS4901B Functional Block Diagram
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
2 of 102
X1 X2 VID_STD[5:0] GENLOCK LOCK_LOST
REF_LOST
HSYNC VSYNC FSYNC 10FID
27MHz Input Reference Rate Identification
and Control ref_rate
Clock Synthesis and Control
Flywheel and Video Timing Generator
Clock Phase Adjust.