HMC7043

Data Sheet High Performance, 3.2 GHz, 14-Output Fanout Buffer HMC7043 FEATURES JEDEC JESD204B support Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz) Very low noise floor: −155.2 dBc/Hz at 983.04 MHz Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz JESD204B-compatible system reference (SYSREF) pulses 25 ps analog and ½ clock input cycle digital delay independently programmable on each of 14 clock output channels SPI-programmable adjustable noise floor vs. power consumption SYSREF valid interrupt to simplify JESD204B synchronization Supports deterministic synchronization of multiple HMC7043 devices RFSYNCIN pin or SPI-controlled SYNC trigger for output synchronization of JESD204B GPIO alarm/status indicator to determine system health Clock input to support up to 6 GHz 48-lead, 7 mm × 7 mm LFCSP package APPLICATIONS JESD204B clock generation Cellular infrastructure (multicarrier GSM, LTE, W-CDMA) Data converter clocking Phase array reference distribution Microwave baseband cards GENERAL DESCRIPTION The HMC7043 is a high performance clock buffer for the distribution of ultralow phase noise references for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio...