Document
74LVC2G126-Q100
Bus buffer/line driver; 3-state
Rev. 1 — 13 May 2015
Product data sheet
1. General description
The 74LVC2G126-Q100 is a dual non-inverting buffer/line driver with 3-state outputs. An output enable input (pin nOE) controls each 3-state output. A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G126-Q100 as a translator in a mixed 3.3 V and 5 V environment.
It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V
NXP Semiconductors
74LVC2G126-Q100
Bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
74LVC2G126DP-Q100 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
74LVC2G126DC-Q100 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
4. Marking
Version SOT505-2
SOT765-1
Table 2. Marking codes Type number 74LVC2G126DP-Q100 74LVC2G126DC-Q100
Marking code[1] V26 V26
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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Fig 1. Logic symbol
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6. Pinning information
6.1 Pinning
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Fig 2. Logic diagram (one gate)
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Fig 3. Pin configuration SOT505-2 and SOT765-1
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74LVC2G126_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 14
NXP Semiconductors
74LVC2G126-Q100
Bus buffer/line driver; 3-state
6.2 Pin description
Table 3. Pin description Symbol 1OE, 2OE 1A, 2A 1Y, 2Y GND VCC
Pin 1, 7 2, 5 6, 3 4 8
7. Functional description
Description output enable input (active HIGH) data input data output ground (0 V) supply voltage
Table 4. Input nOE H H L
Function table[1]
nA L H X
Output nY L H Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage
VI < 0 V
VO > VCC or VO < 0 V Active mode Power-down mode
0.5
50
[1] 0.5
-
[1] 0.5
[1][2]
0.5
+6.5 -
+6.5 50 VCC + 0.5 +6.5
V mA V mA V V
IO ICC IGND Ptot Tstg
output current supply current ground current total power dissipation storage temperature
VO = 0 V to VCC Tamb = 40 C to +125 C
100 [3] 65
50 +100
300 +150
mA mA mA mW C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 packages: above 55 C, the value of Ptot derates linearly at 2.5 mW/K.
For VSSOP8 packages: above 110 C, the value of Ptot derates linearly at 8.0 mW/K.
74LVC2G126_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 14
NXP Semiconductors
74LVC2G126-Q100
Bus buffer/line driver; 3-state
9. Recommended operating conditions
Table 6. Symbol VCC VI VO
Operating conditions Parameter supply voltage input voltage output voltage
Tamb t/V
ambient temperature input transition rise and fall rate
10. Static characteristics
Conditions
Active mode VCC = 0 V; Power-down mode VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V
Min Max Unit 1.65 5.5 V
0 5.5 V 0 VCC V 0 5.5 V 40.