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74LVC2G86 Dataheets PDF



Part Number 74LVC2G86
Manufacturers NXP
Logo NXP
Description Dual 2-input EXCLUSIVE-OR gate
Datasheet 74LVC2G86 Datasheet74LVC2G86 Datasheet (PDF)

74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 11 — 8 April 2013 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device whe.

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74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 11 — 8 April 2013 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant inputs for interfacing with 5 V logic  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  24 mA output drive (VCC = 3.0 V)  CMOS low-power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C NXP Semiconductors 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVC2G86DP 40 C to +125 C TSSOP8 74LVC2G86DC 40 C to +125 C VSSOP8 74LVC2G86GT 40 C to +125 C XSON8 74LVC2G86GF 40 C to +125 C XSON8 74LVC2G86GD 40 C to +125 C XSON8 74LVC2G86GM 40 C to +125 C XQFN8 74LVC2G86GN 40 C to +125 C XSON8 74LVC2G86GS 40 C to +125 C XSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1  1.95  0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35  1  0.5 mm plastic extremely thin small outline package; no leads; 8 terminals; body 3  2  0.5 mm plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6  1.6  0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.2  1.0  0.35 mm extremely thin small outline package; no leads; 8 terminals; body 1.35  1.0  0.35 mm Version SOT505-2 SOT765-1 SOT833-1 SOT1089 SOT996-2 SOT902-2 SOT1116 SOT1203 4. Marking Table 2. Marking codes Type number 74LVC2G86DP 74LVC2G86DC 74LVC2G86GT 74LVC2G86GF 74LVC2G86GD 74LVC2G86GM 74LVC2G86GN 74LVC2G86GS Marking code[1] V86 V86 V86 VH V86 V86 VH VH [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 8 April 2013 © NXP B.V. 2013. All rights reserved. 2 of 21 NXP Semiconductors 5. Functional diagram 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 1A 1Y 1B 2A 2Y 2B 001aah760 Fig 1. Logic symbol =1 =1 001aah761 Fig 2. IEC logic s.


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