Document
PI6C557-03AQ
PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications
Features
ÎÎPCIe® 2.0 compliant àà Phase jitter - 2.1ps RMS (typ)
ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V Current mode differential pair ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎSpread of -0.5%, -0.75%, and no spread ÎÎAEC-Q100 qualified ÎÎSpread Bypass option available ÎÎSpread and frequency selection via external pins ÎÎPackaging: (Pb-free and Green)
àà 16-pin TSSOP (L16)
Description
The PI6C557-03AQ is a spread spectrum clock generator compliant to PCI Express® 2.0 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce Electromagnetic Interference (EMI).
The PI6C557-03AQ provides two differential (HCSL) or LVDS spread spectrum outputs. The PI6C557-03AQ is configured to select spread and clock selection. Using Pericom's patented PhaseLocked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It also provides spread selection of -0.5%, -0.75%, and no spread.
Block Diagram
Pin Configuration (16-Pin TSSOP)
SS1:SS0 2
S1:S0 2
X1/CLK 25 MHz crystal or clock X2
Pulling Capacitors
VDD 2
Control Logic
Phase Lock Loop
Crystal Driver
2 GND
RR OE
CLK0 CLK0
CLK1 CLK1
S0 S1 SS0 X1/CLK X2 OE GNDX SS1
1 2 3 4 5 6 7 8
16 VDDX 15 CLK0 14 CLK0 13 GNDA 12 VDDA 11 CLK1 10 CLK1
9 IREF
All trademarks are property of their respective owners.
14-0076
1
www.pericom.com
PI6C557-03AQ
Rev A
05/22/14
PI6C557-03AQ
PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications
Pin Description
Pin # Pin Name
1 S0 2 S1 3 SS0 4 X1/CLK 5 X2 6 OE 7 GNDX 8 SS1 9 IREF 10 CLK1 11 CLK1 12 VDDA 13 GNDA 14 CLK0 15 CLK0 16 VDDX
I/O Type
Input Input Input Input Output Input Power Input Output Output Output Power Power Output Output Power
Description
Select pin 0 (Internal pull-up resistor). See Table 1. Select pin 1 (Internal pull-up resistor). See Table 1. Spread Select pin 0 (Internal pull-up resistor). See Table 2. Crystal or clock input. Connect to a 25MHz crystal or single ended clock. Crystal connection. Leave unconnected for clock input. Output enable. Internal pull-up resistor. Crystal ground pin. Spread Select pin 1 (Internal pull-up resistor). See Table 2. Precision resistor attached to this pin is connected to the internal current reference. HCSL compliment clock output HCSL clock output Connect to a +3.3V source. Output and analog circuit ground. HCSL compliment clock output HCSL clock output Connect to a +3.3V source.
Table 1: Output Select Table
S1 S0
00 01 10 11
CLK(MHz)
25 100 125 200
Table 2: Spread Selection Table
SS1 SS0
00 01 10 11
Spread
No Spread Down -0.5 Down -0.75 No Spread
All trademarks are property of their respective owners.
14-0076
2
www.pericom.com
PI6C557-03AQ
Rev A
05/22/14
PI6C557-03AQ
PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications
Application Information
Output Structures
Decoupling Capacitors Decoupling capacitors of 0.01μF should be connected between each VDD pin and the ground plane and placed as close to the VDD pin as possible.
Crystal Use a 25MHz fundamental mode parallel resonant crystal with less than 300PPM of error across temperature.
Crystal Capacitors CL = Crystals's load capacitance in pF Crystal Capacitors (pF) = (CL - 8) *2 For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pF. (16-8)*2=16.
Current Source (IREF) Reference Resistor - RR If board target trace impedance is 50Ω, then RR = 475Ω providing an IREF of 2.32 mA. The output current (IOH) is 6*IREF.
Output Termination The PCI Express differential clock outputs of the PI6C557-03AQ are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI Express Layout Guidelines section.
The PI6C557-03AQ can be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.
IREF =2.3mA
6*IREF
See Output Termination RR=475 Ω Sections
All trademarks are property of their respective owners.
14-0076
3
www.pericom.com
PI6C557-03AQ
Rev A
05/22/14
PI6C557-03AQ
PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications
PCI Express Layout Guidelines Common Recommendations for Differential Routing
L1 length, route as non-coupled 50Ω trace. L2 length, route as non-coupled 50Ω trace. L3 length, route as non-coupled 50Ω trace. RS RT
Differential Routing on a Single PCB L4 length, route as coupled microstrip 100Ω differential trace. L4 length, route as coupled stripline 100Ω differential trace.
Differential Routing to a PCI Express connector L4 length, route as coupled microstrip 100Ω differential trace. L4 length, route as coupled stripline 100Ω differential.