CY62146GSL

CY62146G/CY62146GE CY62146GSL/CY62146GESL MoBL® 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features ■ High speed: 45 ns/55 ns ■ Ultra-low standby power ❐ Typical standby current: 3.5 A ❐ Maximum standby current: 8.7 A ■ Embedded ECC for single-bit error correction[1] ■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V ■ 1.0-V data retention ■ TTL-compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages Functional Description CY62146G/CY62146GE and CY62146GSL/CY62146GESL are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62146GE/CY62146GESL device includes an ERR pin that signals an error-detection and correction event during a read cycle. The CY62146GSL/CY62146GESL[1] device supports a wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH. Data writes are performed by asserting the Write Enable (WE) input LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Lo...