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CY7C1386S Dataheets PDF



Part Number CY7C1386S
Manufacturers Cypress
Logo Cypress
Description 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM
Datasheet CY7C1386S DatasheetCY7C1386S Datasheet (PDF)

CY7C1386S 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.4 ns (for 167 MHz device) ■ Provides high-performance 3-1-1-1 acces.

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CY7C1386S 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM 18-Mbit (512 K × 36) Pipelined DCD Sync SRAM Features ■ Supports bus operation up to 167 MHz ■ Available speed grade is 167 MHz ■ Registered inputs and outputs for pipelined operation ■ Optimal for performance (double-cycle deselect) ■ Depth expansion without wait state ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 3.4 ns (for 167 MHz device) ■ Provides high-performance 3-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed writes ■ Asynchronous output enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP ■ ZZ sleep mode option Functional Description The CY7C1386S SRAM integrates 512 K × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see Pin Configurations on page 4 and Truth Table on page 8 for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW writes all bytes. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1386S operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Description 167 MHz 3.4 275 70 Unit ns mA mA Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-43823 Rev. *E • San Jose, CA 95134-1709 • 408-943-2600 Revised April 22, 2013 CY7C1386S Logic Block Diagram – CY7C1386S A0,A1,A MODE ADV CLK ADSC ADSP BW D BW C BW B BW A BWE GW CE 1 CE 2 CE 3 OE ZZ ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 DQ D,DQP D BYTE WRITE REGISTER DQ c,DQP C BYTE WRITE REGISTER DQ B,DQP B BYTE WRITE REGISTER DQ A,DQP A BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE CONTROL DQ D,DQP D BYTE WRITE DRIVER DQ c,DQP C BYTE WRITE DRIVER DQ B,DQP B BYTE WRITE DRIVER DQ A,DQP A BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D INPUT REGISTERS Document Number: 001-43823 Rev. *E Page 2 of 22 CY7C1386S Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 5 Functional Overview ........................................................ 6 Single Read Accesses ................................................ 6 Single Write Accesses Initiated by ADSP ................... 6 Single Write Accesses Initiated by ADSC ................... 6 Burst Sequences ......................................................... 7 Sleep Mode ................................................................. 7 Interleaved Burst Address Table ................................. 7 Linear Burst Address Table ......................................... 7 ZZ Mode Electrical Characteristics .............................. 7 Truth Table ........................................................................ 8 Truth Table for Read/Write .............................................. 9 Maximum Ratings ........................................................... 10 Operating Range ............................................................. 10 Electrical Characteristics ............................................... 10 Capacitance .................................................................... 11 Thermal Resistance ........................................................ 11 AC Test Loads and Waveforms ..................................... 11 Switching Characteristics .............................................. 12 Switching Waveforms .................................................... 13 Ordering Information .....................................................


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