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UT54ACS373 Dataheets PDF



Part Number UT54ACS373
Manufacturers Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology
Description Octal Transparent Latches
Datasheet UT54ACS373 DatasheetUT54ACS373 Datasheet (PDF)

Standard Products UT54ACS373/UT54ACTS373 Octal Transparent Latches with Three-State Outputs Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 8 latches in a single package ‰ Three-state bus-driving true outputs ‰ Full parallel access for loading ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 20-pin DIP - 20-lead flatpack ‰ UT54ACS373 - SMD 5962-96588 ‰ UT54ACTS373 - SMD 5962-96589 DESCRIPTI.

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Standard Products UT54ACS373/UT54ACTS373 Octal Transparent Latches with Three-State Outputs Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 8 latches in a single package ‰ Three-state bus-driving true outputs ‰ Full parallel access for loading ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 20-pin DIP - 20-lead flatpack ‰ UT54ACS373 - SMD 5962-96588 ‰ UT54ACTS373 - SMD 5962-96589 DESCRIPTION The UT54ACS373 and the UT54ACTS373 are 8-bit latches with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers. The eight latches are transparent D latches. While the enable (C) is high the Q outputs will follow the data (D) inputs. When the enable is taken low, the Q outputs will be latched at the levels that were set up at the D inputs. An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without need for interface or pull-up components. The output control OC does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE INPUTS OUTPUT OC C nD nQ L H HH L H LL L L X nQ0 H X X Z1 Note: 1. Data may be latched internally. PINOUTS 20-Pin DIP Top View OC 1 20 1Q 2 19 1D 3 18 2D 4 17 2Q 5 16 3Q 6 3D 7 15 14 4D 8 13 4Q 9 12 VSS 10 11 VDD 8Q 8D 7D 7Q 6Q 6D 5D 5Q C 20-Lead Flatpack Top View OC 1Q 1D 2D 2Q 3Q 3D 4D 4Q VSS LOGIC SYMBOL (1) OC (11) C EN C1 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VDD 8Q 8D 7D 7Q 6Q 6D 5D 5Q C 1D (3) 2D (4) 3D (7) 4D (8) 5D (13) 6D (14) 7D (17) 8D (18) 1D (2) (5) 1Q 2Q (6) 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 LOGIC DIAGRAM 8D (18) 7D (17) 6D 5D (14) (13) 4D (8) 3D (7) 2D (4) 1D C OC (3) (11) (1) DC DC DC DC D C DC DC DC Q QQ Q Q Q QQ (19) (16) (15) (12) (9) (6) (5) (2) 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 2 OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD VI/O TSTG TJ TLS ΘJC II PD Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 ±10 1 V V °C °C °C °C/W mA W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 ×C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN VOL VOH IOZ IOS IOL IOH Ptotal PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Three-state output leakage current Short-circuit output current 2 ,4 ACTS/ACS Output current10 (Sink) Output current10 (Source) Power dissipation 2, 8, 9 IDDQ ΔIDDQ Quiescent Supply Current Quiescent Supply Current Delta ACTS CIN COUT Input capacitance 5 Output capacitance 5 CONDITION VIN = VDD or VSS IOL = 8.0mA IOL = 100μA IOH = -8.0mA IOH = -100μA VO = VDD and VSS VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V ƒ = 1MHz @ 0V ƒ = 1MHz @ 0V MIN .5VDD .7VDD -1 MAX UNIT 0.8 .3VDD V V 1 μA 0.40 V 0.25 .7VDD VDD - 0.25 -20 -200 8 20 200 V μA mA mA -8 mA 1.9 mW/ MHz 10 μA 1.6 mA 15 pF 15 pF 4 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, fo.


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