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UT54ACTS34 Dataheets PDF



Part Number UT54ACTS34
Manufacturers Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology
Description Hex Noninverting Buffers
Datasheet UT54ACTS34 DatasheetUT54ACTS34 Datasheet (PDF)

Standard Products UT54ACS34/UT54ACTS34 Hex Noninverting Buffers Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS34 - SMD 5962-96530 ‰ UT54ACTS34 - SMD 5962-96531 DESCRIPTION The UT54ACS34 and the UT54ACTS34 are hex noninvertering buffers. The circuits perform the Boolean functions Y = A. The devices are ch.

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Standard Products UT54ACS34/UT54ACTS34 Hex Noninverting Buffers Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS34 - SMD 5962-96530 ‰ UT54ACTS34 - SMD 5962-96531 DESCRIPTION The UT54ACS34 and the UT54ACTS34 are hex noninvertering buffers. The circuits perform the Boolean functions Y = A. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE INPUT A H L OUTPUT Y H L LOGIC SYMBOL PINOUTS 14-Pin DIP Top View A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 4 11 A5 A3 5 10 Y5 Y3 6 9 A4 VSS 7 8 Y4 14-Lead Flatpack Top View A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 4 11 A5 A3 5 10 Y5 Y3 69 A4 VSS 78 Y4 LOGIC DIAGRAM (1) A1 (3) A2 (5) A3 (9) A4 (11) A5 (13) A6 1 (2) Y1 (4) Y2 (6) Y3 (8) Y4 (10) Y5 (12) Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 1 OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O TSTG TJ TLS ΘJC II Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current -.3 to VDD +.3 -65 to +150 +175 +300 20 ±10 V °C °C °C °C/W mA PD Maximum power dissipation 1W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V °C 2 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Ptotal PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Short-circuit output current 2 ,4 ACTS/ACS Output current10 (Sink) Output current10 (Source) Power dissipation 2, 8, 9 IDDQ ΔIDDQ Quiescent Supply Current Quiescent Supply Current Delta ACTS CIN COUT Input capacitance 5 Output capacitance 5 CONDITION VIN = VDD or VSS IOL = 8.0mA IOL = 100μA IOH = -8.0mA IOH = -100μA VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V ƒ = 1MHz @ 0V ƒ = 1MHz @ 0V MIN .5VDD .7VDD -1 MAX 0.8 .3VDD UNIT V V 1 μA 0.40 V 0.25 .7VDD VDD - 0.25 -200 8 200 V mA mA -8 mA 1.8 mW/ MHz 10 μA 1.6 mA 15 pF 15 pF 3 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 4 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn tPLH Input to Yn 1 11 ns 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation .


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