UT8Q512E

Standard Products UT8Q512E 512K x 8 RadTol SRAM Data Sheet November 11, 2008 FEATURES ‰ 20ns maximum (3.3 volt supply) address access time ‰ Asynchronous operation for compatibility with industry- standard 512K x 8 SRAMs ‰ TTL compatible inputs and output levels, three-state bidirectional data bus ‰ Operational environment: - Total dose: 50 krads(Si) - SEL Immune 110 MeV-cm2/mg - SEU LETTH(0.25) = 52 cm2 MeV - Saturated Cross Section 2.8E-8 cm2/bit -<1.1E-9 errors/bit-day, Adams 90% worst case environment geosynchronous orbit ‰ Packaging: - 36-lead ceramic flatpack (3.831 grams) ‰ Standard Microcircuit Drawing 5962-99607 - QML Q and V compliant part INTRODUCTION The UT8Q512E RadTol product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (E) and Write Enable (W) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E HIGH), th...