GS81302T19E

GS81302T07/10/19/37E-450/400/350/333/300 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features 2.0 Clock Latency Simultaneous Read and Write SigmaDDR™ Interface Common I/O bus JEDEC-standard pinout and package Double Data Rate interface Byte Write controls sampled at data-in time Burst of 2 Read and Write On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation with self-timed Late Write Fully coherent read and write pipelines ZQ pin for programmable output drive strength Data Valid pin (QVLD) Support IEEE 1149.1 JTAG-compliant Boundary Scan 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview The GS81302T07/10/19/37E are built in compliance with the SigmaDDR-II+ SRAM pinout standard for Common I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302T07/10/19/37E SigmaDDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS81302T07/10/19/37E SigmaDDR-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, ...